| Commit message (Expand) | Author | Age | Files | Lines |
|---|
| ... | |
| * | Progress in Verific bindings | Clifford Wolf | 2014-03-13 | 1 | -10/+65 |
| * | Copy Verific vdbs files to Yosys "share" data directory | Clifford Wolf | 2014-03-13 | 2 | -8/+23 |
| * | Added test_navre.ys for verific frontend | Clifford Wolf | 2014-03-13 | 1 | -0/+17 |
| * | Merged OSX fixes from Siesh1oo with some modifications | Clifford Wolf | 2014-03-13 | 1 | -0/+1 |
| * | Merged a few fixes for non-posix systems from github.com/Siesh1oo/yosys | Clifford Wolf | 2014-03-11 | 1 | -4/+12 |
| * | Added support for `line compiler directive | Clifford Wolf | 2014-03-11 | 1 | -0/+11 |
| * | Improved verific command (added support for some operators) | Clifford Wolf | 2014-03-10 | 1 | -2/+160 |
| * | Improvements in verific command | Clifford Wolf | 2014-03-10 | 1 | -59/+39 |
| * | Added "verific" command | Clifford Wolf | 2014-03-09 | 2 | -0/+489 |
| * | Bugfix in ilang frontend autoidx recovery | Clifford Wolf | 2014-03-07 | 1 | -2/+2 |
| * | Fixed gcc compiler warning | Clifford Wolf | 2014-03-06 | 1 | -1/+2 |
| * | Include id2ast pointers when dumping AST | Clifford Wolf | 2014-03-05 | 1 | -0/+6 |
| * | Fixed merging of compatible wire decls in AST frontend | Clifford Wolf | 2014-03-05 | 1 | -1/+4 |
| * | Bugfix in recursive AST simplification | Clifford Wolf | 2014-03-05 | 1 | -10/+22 |
| * | Fixed vhdl2verilog temp dir name | Clifford Wolf | 2014-03-01 | 1 | -1/+1 |
| * | Fixed vhdl2verilog help message | Clifford Wolf | 2014-03-01 | 1 | -3/+2 |
| * | Fixed bit-extending in $mux argument (use $bu0 instead of $pos) | Clifford Wolf | 2014-02-26 | 1 | -5/+5 |
| * | Don't blow up constants unneccessarily in Verilog frontend | Clifford Wolf | 2014-02-24 | 1 | -1/+1 |
| * | Fixed bug in generation of undefs for $memwr MUXes | Clifford Wolf | 2014-02-22 | 1 | -4/+6 |
| * | Added vhdl2verilog | Clifford Wolf | 2014-02-21 | 2 | -0/+155 |
| * | Cleanups in handling of read_verilog -defer and -icells | Clifford Wolf | 2014-02-20 | 1 | -6/+7 |
| * | Added Verilog support for "`default_nettype none" | Clifford Wolf | 2014-02-17 | 8 | -8/+31 |
| * | Added a warning note about error reporting to read_verilog help message | Clifford Wolf | 2014-02-16 | 1 | -0/+5 |
| * | Improved support for constant functions | Clifford Wolf | 2014-02-16 | 1 | -1/+50 |
| * | Added ff and latch support to read_liberty | Clifford Wolf | 2014-02-15 | 1 | -40/+254 |
| * | Bugfix in expression parser of read_liberty | Clifford Wolf | 2014-02-15 | 1 | -2/+1 |
| * | Correctly convert constants to RTLIL (fixed undef handling) | Clifford Wolf | 2014-02-15 | 1 | -11/+1 |
| * | Added liberty frontend | Clifford Wolf | 2014-02-15 | 2 | -0/+362 |
| * | Be more conservative with new const-function code | Clifford Wolf | 2014-02-14 | 1 | -1/+5 |
| * | Added support for FOR loops in function calls in parameters | Clifford Wolf | 2014-02-14 | 3 | -0/+43 |
| * | Created basic support for function calls in parameter values | Clifford Wolf | 2014-02-14 | 4 | -49/+184 |
| * | Implemented read_verilog -defer | Clifford Wolf | 2014-02-13 | 3 | -59/+90 |
| * | Added support for functions returning integer | Clifford Wolf | 2014-02-12 | 1 | -2/+12 |
| * | renamed ilang "scope error" to "ilang error" | Clifford Wolf | 2014-02-11 | 1 | -9/+9 |
| * | Improved ilang parser error messages | Clifford Wolf | 2014-02-09 | 1 | -9/+9 |
| * | Fixed gcc compiler warnings with release build | Clifford Wolf | 2014-02-06 | 1 | -1/+1 |
| * | Added read_verilog -setattr | Clifford Wolf | 2014-02-05 | 1 | -0/+15 |
| * | Fixed bug in sequential sat proofs and improved handling of asserts | Clifford Wolf | 2014-02-04 | 1 | -0/+2 |
| * | Added TRANSPARENT parameter to $memrd (and RD_TRANSPARENT to $mem) | Clifford Wolf | 2014-02-03 | 1 | -0/+1 |
| * | Added support for blanks after -I and -D in read_verilog | Clifford Wolf | 2014-02-02 | 1 | -7/+20 |
| * | Fixed comment/eol parsing in ilang frontend | Clifford Wolf | 2014-02-01 | 2 | -22/+25 |
| * | Added constant size expression support of sized constants | Clifford Wolf | 2014-02-01 | 5 | -0/+44 |
| * | Bugfix in name resolution with generate blocks | Clifford Wolf | 2014-01-30 | 1 | -1/+1 |
| * | Added read_verilog -icells option | Clifford Wolf | 2014-01-29 | 4 | -6/+20 |
| * | Fixed handling of unsized constants in verilog frontend | Clifford Wolf | 2014-01-24 | 1 | -2/+2 |
| * | Fixed algorithmic complexity of AST simplification of long expressions | Clifford Wolf | 2014-01-20 | 3 | -6/+13 |
| * | Added $assert cell | Clifford Wolf | 2014-01-19 | 2 | -0/+92 |
| * | Added Verilog parser support for asserts | Clifford Wolf | 2014-01-19 | 4 | -3/+12 |
| * | Fixed parsing of verilog macros at end of line | Clifford Wolf | 2014-01-18 | 1 | -1/+1 |
| * | Added verilog_defaults command | Clifford Wolf | 2014-01-17 | 1 | -0/+66 |
