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| author | Clifford Wolf <clifford@clifford.at> | 2014-02-22 17:08:00 +0100 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2014-02-22 17:08:00 +0100 |
| commit | f8c9143b2b232e2f22e6cfbf9c431b2a1b756afa (patch) | |
| tree | 9ea61f1042c4c505aecccc0d72f0537ae6ece5cb /frontends | |
| parent | 548519875bbffda02c5c7a891ce67fd3738d6e6f (diff) | |
| download | yosys-f8c9143b2b232e2f22e6cfbf9c431b2a1b756afa.tar.gz yosys-f8c9143b2b232e2f22e6cfbf9c431b2a1b756afa.tar.bz2 yosys-f8c9143b2b232e2f22e6cfbf9c431b2a1b756afa.zip | |
Fixed bug in generation of undefs for $memwr MUXes
Diffstat (limited to 'frontends')
| -rw-r--r-- | frontends/ast/simplify.cc | 10 |
1 files changed, 6 insertions, 4 deletions
diff --git a/frontends/ast/simplify.cc b/frontends/ast/simplify.cc index 5e37911d3..55ed28b01 100644 --- a/frontends/ast/simplify.cc +++ b/frontends/ast/simplify.cc @@ -1088,14 +1088,16 @@ skip_dynamic_range_lvalue_expansion:; current_scope[wire_en->str] = wire_en; while (wire_en->simplify(true, false, false, 1, -1, false, false)) { } - std::vector<RTLIL::State> x_bits; + std::vector<RTLIL::State> x_bits_addr, x_bits_data; + for (int i = 0; i < addr_bits; i++) + x_bits_addr.push_back(RTLIL::State::Sx); for (int i = 0; i < mem_width; i++) - x_bits.push_back(RTLIL::State::Sx); + x_bits_data.push_back(RTLIL::State::Sx); - AstNode *assign_addr = new AstNode(AST_ASSIGN_LE, new AstNode(AST_IDENTIFIER), mkconst_bits(x_bits, false)); + AstNode *assign_addr = new AstNode(AST_ASSIGN_LE, new AstNode(AST_IDENTIFIER), mkconst_bits(x_bits_addr, false)); assign_addr->children[0]->str = id_addr; - AstNode *assign_data = new AstNode(AST_ASSIGN_LE, new AstNode(AST_IDENTIFIER), mkconst_bits(x_bits, false)); + AstNode *assign_data = new AstNode(AST_ASSIGN_LE, new AstNode(AST_IDENTIFIER), mkconst_bits(x_bits_data, false)); assign_data->children[0]->str = id_data; AstNode *assign_en = new AstNode(AST_ASSIGN_LE, new AstNode(AST_IDENTIFIER), mkconst_int(0, false, 1)); |