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| author | Clifford Wolf <clifford@clifford.at> | 2014-02-15 15:42:10 +0100 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2014-02-15 15:42:10 +0100 |
| commit | 5e39e6ece28e1145a04e8f00f9ac4f5d9a738acf (patch) | |
| tree | 9c10001c89c92beebafaf3f8411316346d332f62 /frontends | |
| parent | 30379ea20d0f07016f24652336e85493bcff2f18 (diff) | |
| download | yosys-5e39e6ece28e1145a04e8f00f9ac4f5d9a738acf.tar.gz yosys-5e39e6ece28e1145a04e8f00f9ac4f5d9a738acf.tar.bz2 yosys-5e39e6ece28e1145a04e8f00f9ac4f5d9a738acf.zip | |
Correctly convert constants to RTLIL (fixed undef handling)
Diffstat (limited to 'frontends')
| -rw-r--r-- | frontends/ast/genrtlil.cc | 12 |
1 files changed, 1 insertions, 11 deletions
diff --git a/frontends/ast/genrtlil.cc b/frontends/ast/genrtlil.cc index d92da4000..12fe23fd8 100644 --- a/frontends/ast/genrtlil.cc +++ b/frontends/ast/genrtlil.cc @@ -905,18 +905,8 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint) if (width_hint < 0) detectSignWidth(width_hint, sign_hint); - RTLIL::SigChunk chunk; - chunk.wire = NULL; - chunk.data.bits = bits; - chunk.width = bits.size(); - chunk.offset = 0; - - RTLIL::SigSpec sig; - sig.chunks.push_back(chunk); - sig.width = chunk.width; - is_signed = sign_hint; - return sig; + return RTLIL::SigSpec(bitsAsConst(width_hint, sign_hint)); } // simply return the corresponding RTLIL::SigSpec for an AST_IDENTIFIER node |