| Commit message (Expand) | Author | Age | Files | Lines |
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| * | Merge pull request #610 from udif/udif_specify_round2 | Clifford Wolf | 2018-08-23 | 1 | -16/+39 |
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| | * | Fixed all known specify/endspecify issues, without breaking 'make test'. | Udi Finkelstein | 2018-08-20 | 1 | -12/+12 |
| | * | Yosys can now parse https://github.com/verilog-to-routing/vtr-verilog-to-rout... | Udi Finkelstein | 2018-08-20 | 1 | -10/+22 |
| | * | A few minor enhancements to specify block parsing. | Udi Finkelstein | 2018-08-15 | 1 | -2/+13 |
| * | | Added -no_dump_ptr flag for AST dump options in 'read_verilog' | Udi Finkelstein | 2018-08-23 | 1 | -1/+9 |
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| * | Merge pull request #591 from hzeller/virtual-override | Clifford Wolf | 2018-08-15 | 1 | -6/+6 |
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| | * | Consistent use of 'override' for virtual methods in derived classes. | Henner Zeller | 2018-07-20 | 1 | -6/+6 |
| * | | Merge pull request #513 from udif/pr_reg_wire_error | Clifford Wolf | 2018-08-15 | 2 | -2/+7 |
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| | * | | Modified errors into warnings | Udi Finkelstein | 2018-06-05 | 1 | -0/+1 |
| | * | | This PR should be the base for discussion, do not merge it yet! | Udi Finkelstein | 2018-03-11 | 2 | -2/+6 |
| * | | | Merge pull request #562 from udif/pr_fix_illegal_port_decl | Clifford Wolf | 2018-08-15 | 1 | -3/+6 |
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| | * | | Detect illegal port declaration, e.g input/output/inout keyword must be the f... | Udi Finkelstein | 2018-06-06 | 1 | -3/+6 |
| * | | | Convert more log_error() to log_file_error() where possible. | Henner Zeller | 2018-07-20 | 1 | -5/+3 |
| * | | | Use log_file_warning(), log_file_error() functions. | Henner Zeller | 2018-07-20 | 1 | -5/+3 |
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| * | | Support SystemVerilog `` extension for macros | Jim Paris | 2018-05-17 | 1 | -1/+5 |
| * | | Skip spaces around macro arguments | Jim Paris | 2018-05-17 | 1 | -0/+1 |
| * | | Replace -ignore_redef with -[no]overwrite | Clifford Wolf | 2018-05-03 | 1 | -6/+17 |
| * | | Support more character literals | Dan Gisselquist | 2018-05-03 | 1 | -1/+9 |
| * | | Add statement labels for immediate assertions | Clifford Wolf | 2018-04-13 | 1 | -18/+21 |
| * | | Allow "property" in immediate assertions | Clifford Wolf | 2018-04-12 | 1 | -17/+20 |
| * | | Add read_verilog anyseq/anyconst/allseq/allconst attribute support | Clifford Wolf | 2018-04-06 | 1 | -1/+33 |
| * | | First draft of Verilog parser support for specify blocks and parameters. | Udi Finkelstein | 2018-03-27 | 2 | -2/+170 |
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| * | Add $allconst and $allseq cell types | Clifford Wolf | 2018-02-23 | 1 | -1/+3 |
| * | Add support for "yosys -E" | Clifford Wolf | 2018-01-07 | 1 | -2/+4 |
| * | Bugfix in verilog_defaults argument parser | Clifford Wolf | 2017-12-24 | 1 | -1/+1 |
| * | Add Verilog "automatic" keyword (ignored in synthesis) | Clifford Wolf | 2017-11-23 | 2 | -13/+18 |
| * | Accept real-valued delay values | Clifford Wolf | 2017-11-18 | 1 | -0/+1 |
| * | Accommodate Windows-style paths during include-file processing. | William D. Jones | 2017-11-14 | 1 | -4/+20 |
| * | Resolved classical Bison IF/THEN/ELSE shift/reduce conflict using the textboo... | Udi Finkelstein | 2017-09-30 | 1 | -3/+5 |
| * | Minor coding style fix | Clifford Wolf | 2017-09-26 | 1 | -1/+1 |
| * | Merge branch 'master' of https://github.com/combinatorylogic/yosys into combi... | Clifford Wolf | 2017-09-26 | 1 | -41/+69 |
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| | * | Adding support for string macros and macros with arguments after include | combinatorylogic | 2017-09-21 | 1 | -41/+69 |
| * | | Fix ignoring of simulation timings so that invalid module parameters cause sy... | Clifford Wolf | 2017-09-26 | 2 | -4/+2 |
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| * | Add a paragraph about pre-defined macros to read_verilog help message | Clifford Wolf | 2017-07-21 | 1 | -0/+4 |
| * | Fix generation of vlogtb output in yosys-smtbmc for "rand reg" and "rand cons... | Clifford Wolf | 2017-06-07 | 1 | -0/+1 |
| * | Fix handling of Verilog ~& and ~| operators | Clifford Wolf | 2017-06-01 | 1 | -0/+8 |
| * | Add support for localparam in module header | Clifford Wolf | 2017-04-30 | 1 | -1/+7 |
| * | Add support for `resetall compiler directive | Clifford Wolf | 2017-04-26 | 1 | -0/+7 |
| * | Fix verilog pre-processor for multi-level relative includes | Clifford Wolf | 2017-03-14 | 1 | -4/+26 |
| * | Allow $anyconst, etc. in non-formal SV mode | Clifford Wolf | 2017-03-01 | 1 | -1/+1 |
| * | Add $live and $fair cell types, add support for s_eventually keyword | Clifford Wolf | 2017-02-25 | 2 | -1/+28 |
| * | Add support for SystemVerilog unique, unique0, and priority case | Clifford Wolf | 2017-02-23 | 2 | -4/+25 |
| * | Added SystemVerilog support for ++ and -- | Clifford Wolf | 2017-02-23 | 2 | -1/+12 |
| * | Add checker support to verilog front-end | Clifford Wolf | 2017-02-09 | 2 | -11/+24 |
| * | Add SV "rand" and "const rand" support | Clifford Wolf | 2017-02-08 | 2 | -8/+28 |
| * | Further improve cover() support | Clifford Wolf | 2017-02-04 | 1 | -0/+6 |
| * | Add $cover cell type and SVA cover() support | Clifford Wolf | 2017-02-04 | 2 | -1/+8 |
| * | Add "enum" and "typedef" lexer support | Clifford Wolf | 2017-01-17 | 2 | -1/+4 |
| * | Added "verilog_defines" command | Clifford Wolf | 2016-12-15 | 1 | -0/+60 |
| * | Added support for macros as include file names | Clifford Wolf | 2016-11-28 | 1 | -0/+2 |
