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* Build Verilog parser with -DYYMAXDEPTH=100000, fixes #906Clifford Wolf2019-03-291-0/+2
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Improve read_verilog debug output capabilitiesClifford Wolf2019-03-211-5/+24
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Fix handling of cases that look like sva labels, fixes #862Clifford Wolf2019-03-102-92/+66
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Also add support for labels on sva module items, fixes #699Clifford Wolf2019-03-082-44/+113
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Add support for SVA labels in read_verilogClifford Wolf2019-03-071-23/+79
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Bugfix in Verilog string handlingClifford Wolf2019-01-051-1/+1
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Fix typographical and grammatical errors and inconsistencies.whitequark2019-01-021-3/+3
| | | | | | | | | | | | The initial list of hits was generated with the codespell command below, and each hit was evaluated and fixed manually while taking context into consideration. DIRS="kernel/ frontends/ backends/ passes/ techlibs/" DIRS="${DIRS} libs/ezsat/ libs/subcircuit" codespell $DIRS -S *.o -L upto,iff,thru,synopsys,uint More hits were found by looking through comments and strings manually.
* verilog_parser: Properly handle recursion when processing attributesSylvain Munaut2018-12-141-19/+29
| | | | | | Fixes #737 Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
* Add warning for SV "restrict" without "property"Clifford Wolf2018-11-041-2/+11
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Fix minor typo in error messageClifford Wolf2018-10-251-1/+1
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Rename the generic "Syntax error" message from the Verilog/SystemVerilog ↵Udi Finkelstein2018-10-251-14/+14
| | | | | | | parser into unique, meaningful info on the error. Also add 13 compilation examples that triggers each of these messages.
* Merge pull request #659 from rubund/sv_interfacesClifford Wolf2018-10-182-0/+88
|\ | | | | Support for SystemVerilog interfaces and modports
| * Handle FIXME for modport members without type directly in frontRuben Undheim2018-10-131-6/+8
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| * Support for 'modports' for System Verilog interfacesRuben Undheim2018-10-121-3/+21
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| * Synthesis support for SystemVerilog interfacesRuben Undheim2018-10-122-0/+68
| | | | | | | | This time doing the changes mostly in AST before RTLIL generation
* | ignore protect endprotectargama2018-10-161-0/+3
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* Add "read_verilog -noassert -noassume -assert-assumes"Clifford Wolf2018-09-243-6/+49
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Added support for ommited "parameter" in Verilog-2001 style parameter decl ↵Clifford Wolf2018-09-231-3/+9
| | | | | | in SV mode Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Add "make coverage"Clifford Wolf2018-08-273-6/+5
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Merge pull request #610 from udif/udif_specify_round2Clifford Wolf2018-08-231-16/+39
|\ | | | | More specify/endspecify fixes
| * Fixed all known specify/endspecify issues, without breaking 'make test'.Udi Finkelstein2018-08-201-12/+12
| | | | | | | | | | Some the of parser fixes may look strange but they were needed to avoid shift/reduce conflicts, due to the explicit parentheses in path_delay_value, and the mintypmax values without parentheses
| * Yosys can now parse ↵Udi Finkelstein2018-08-201-10/+22
| | | | | | | | | | | | | | https://github.com/verilog-to-routing/vtr-verilog-to-routing/blob/master/vtr_flow/primitives.v , (specify block ignored). Must use 'read_verilog -defer' due to a parameter not assigned a default value.
| * A few minor enhancements to specify block parsing.Udi Finkelstein2018-08-151-2/+13
| | | | | | | | Just remember specify blocks are parsed but ignored.
* | Added -no_dump_ptr flag for AST dump options in 'read_verilog'Udi Finkelstein2018-08-231-1/+9
|/ | | | | | This option disables the memory pointer display. This is useful when diff'ing different dumps because otherwise the node pointers makes every diff line different when the AST content is the same.
* Merge pull request #591 from hzeller/virtual-overrideClifford Wolf2018-08-151-6/+6
|\ | | | | Consistent use of 'override' for virtual methods in derived classes.
| * Consistent use of 'override' for virtual methods in derived classes.Henner Zeller2018-07-201-6/+6
| | | | | | | | | | | | | | | | | | o Not all derived methods were marked 'override', but it is a great feature of C++11 that we should make use of. o While at it: touched header files got a -*- c++ -*- for emacs to provide support for that language. o use YS_OVERRIDE for all override keywords (though we should probably use the plain keyword going forward now that C++11 is established)
* | Merge pull request #513 from udif/pr_reg_wire_errorClifford Wolf2018-08-152-2/+7
|\ \ | | | | | | Add error checking for reg/wire/logic misuse - PR now passes 'make test' (plus a new test)
| * | Modified errors into warningsUdi Finkelstein2018-06-051-0/+1
| | | | | | | | | | | | No longer false warnings for memories and assertions
| * | This PR should be the base for discussion, do not merge it yet!Udi Finkelstein2018-03-112-2/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | It correctly detects reg/wire mix and incorrect use on blocking,nonblocking assignments within blocks and assign statements. What it DOES'T do: Detect registers connected to output ports of instances. Where it FAILS: memorty nonblocking assignments causes spurious (I assume??) errors on yosys-generated "_ADDR", "_DATA", "EN" signals. You can test it with tests/simple/reg_wire_error.v (look inside for the comments to enable/disable specific lines)
* | | Merge pull request #562 from udif/pr_fix_illegal_port_declClifford Wolf2018-08-151-3/+6
|\ \ \ | |_|/ |/| | Detect illegal port declaration, e.g input/output/inout keyword must …
| * | Detect illegal port declaration, e.g input/output/inout keyword must be the ↵Udi Finkelstein2018-06-061-3/+6
| | | | | | | | | | | | first.
* | | Convert more log_error() to log_file_error() where possible.Henner Zeller2018-07-201-5/+3
| | | | | | | | | | | | | | | Mostly statements that span over multiple lines and haven't been caught with the previous conversion.
* | | Use log_file_warning(), log_file_error() functions.Henner Zeller2018-07-201-5/+3
|/ / | | | | | | Wherever we can report a source-level location.
* | Support SystemVerilog `` extension for macrosJim Paris2018-05-171-1/+5
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* | Skip spaces around macro argumentsJim Paris2018-05-171-0/+1
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* | Replace -ignore_redef with -[no]overwriteClifford Wolf2018-05-031-6/+17
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | Support more character literalsDan Gisselquist2018-05-031-1/+9
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* | Add statement labels for immediate assertionsClifford Wolf2018-04-131-18/+21
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | Allow "property" in immediate assertionsClifford Wolf2018-04-121-17/+20
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | Add read_verilog anyseq/anyconst/allseq/allconst attribute supportClifford Wolf2018-04-061-1/+33
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | First draft of Verilog parser support for specify blocks and parameters.Udi Finkelstein2018-03-272-2/+170
|/ | | | | The only functionality of this code at the moment is to accept correct specify syntax and ignore it. No part of the specify block is added to the AST
* Add $allconst and $allseq cell typesClifford Wolf2018-02-231-1/+3
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Add support for "yosys -E"Clifford Wolf2018-01-071-2/+4
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Bugfix in verilog_defaults argument parserClifford Wolf2017-12-241-1/+1
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* Add Verilog "automatic" keyword (ignored in synthesis)Clifford Wolf2017-11-232-13/+18
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* Accept real-valued delay valuesClifford Wolf2017-11-181-0/+1
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* Accommodate Windows-style paths during include-file processing.William D. Jones2017-11-141-4/+20
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* Resolved classical Bison IF/THEN/ELSE shift/reduce conflict using the ↵Udi Finkelstein2017-09-301-3/+5
| | | | | | textbook solution (Oreilly 'Flex & Bison' page 189)
* Minor coding style fixClifford Wolf2017-09-261-1/+1
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* Merge branch 'master' of https://github.com/combinatorylogic/yosys into ↵Clifford Wolf2017-09-261-41/+69
|\ | | | | | | combinatorylogic-master
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