iCE40/yosys - [no description]

	Commit message (Expand)	Author	Age	Files	Lines
*	Added "make PRETTY=1"	Clifford Wolf	2014-07-24	1	-3/+3
*	fixed parsing of constant with comment between size and value	Clifford Wolf	2014-07-02	1	-0/+7
*	Fixed parsing of TOK_INTEGER (implies TOK_SIGNED)	Clifford Wolf	2014-06-16	1	-5/+11
*	Improved parsing of large integer constants	Clifford Wolf	2014-06-15	1	-11/+28
*	Added handling of real-valued parameters/localparams	Clifford Wolf	2014-06-14	2	-7/+15
*	Added Verilog lexer and parser support for real values	Clifford Wolf	2014-06-13	2	-3/+24
*	Added read_verilog -sv options, added support for bit, logic,	Clifford Wolf	2014-06-12	4	-3/+37
*	Add support for cell arrays	Clifford Wolf	2014-06-07	1	-0/+7
*	made the generate..endgenrate keywords optional	Clifford Wolf	2014-06-06	1	-4/+8
*	added while and repeat support to verilog parser	Clifford Wolf	2014-06-06	2	-1/+29
*	Improved error message for options after front-end filename arguments	Clifford Wolf	2014-06-04	1	-1/+1
*	Fixed clang -Wdeprecated-register warnings	Clifford Wolf	2014-04-20	1	-0/+5
*	Replaced depricated %name-prefix= bison directive	Clifford Wolf	2014-04-20	1	-1/+1
*	Merged OSX fixes from Siesh1oo with some modifications	Clifford Wolf	2014-03-13	1	-0/+1
*	Added support for `line compiler directive	Clifford Wolf	2014-03-11	1	-0/+11
*	Added Verilog support for "`default_nettype none"	Clifford Wolf	2014-02-17	5	-2/+18
*	Added a warning note about error reporting to read_verilog help message	Clifford Wolf	2014-02-16	1	-0/+5
*	Implemented read_verilog -defer	Clifford Wolf	2014-02-13	1	-1/+11
*	Added support for functions returning integer	Clifford Wolf	2014-02-12	1	-2/+12
*	Added read_verilog -setattr	Clifford Wolf	2014-02-05	1	-0/+15
*	Added support for blanks after -I and -D in read_verilog	Clifford Wolf	2014-02-02	1	-7/+20
*	Added constant size expression support of sized constants	Clifford Wolf	2014-02-01	1	-0/+22
*	Added read_verilog -icells option	Clifford Wolf	2014-01-29	1	-1/+9
*	Fixed handling of unsized constants in verilog frontend	Clifford Wolf	2014-01-24	1	-2/+2
*	Added Verilog parser support for asserts	Clifford Wolf	2014-01-19	2	-3/+10
*	Fixed parsing of verilog macros at end of line	Clifford Wolf	2014-01-18	1	-1/+1
*	Added verilog_defaults command	Clifford Wolf	2014-01-17	1	-0/+66
*	Fixed parsing of non-arg macro calls followed by "("	Clifford Wolf	2013-12-27	1	-1/+7
*	Fixed parsing of macros with no arguments and expansion text starting with "("	Clifford Wolf	2013-12-27	1	-1/+2
*	Added proper === and !== support in constant expressions	Clifford Wolf	2013-12-27	2	-3/+11
*	Added elsif preproc support	Clifford Wolf	2013-12-18	1	-1/+14
*	Added support for macro arguments	Clifford Wolf	2013-12-18	1	-23/+75
*	Added AstNode::mkconst_str API	Clifford Wolf	2013-12-05	1	-12/+1
*	Various improvements in support for generate statements	Clifford Wolf	2013-12-04	2	-5/+43
*	Added support for local regs in named blocks	Clifford Wolf	2013-12-04	1	-2/+5
*	Added verilog frontend -ignore_redef option	Clifford Wolf	2013-11-24	1	-1/+10
*	Improved handling of initialized registers	Clifford Wolf	2013-11-23	1	-10/+10
*	Renamed "placeholder" to "blackbox"	Clifford Wolf	2013-11-22	1	-1/+1
*	Fixed O(n^2) performance bug in verilog preprocessor	Clifford Wolf	2013-11-22	1	-1/+1
*	Enable {* .. *} feature per default (removes dependency to REJECT feature in ...	Clifford Wolf	2013-11-22	4	-22/+2
*	Implemented indexed part selects	Clifford Wolf	2013-11-20	2	-0/+14
*	Added "synthesis" in (synopsys\|synthesis) comment support	Clifford Wolf	2013-11-20	1	-6/+6
*	Implemented part/bit select on memory read	Clifford Wolf	2013-11-20	1	-2/+12
*	Added init= attribute for fpga-style reset values	Clifford Wolf	2013-11-20	1	-6/+19
*	Fixed parsing of module arguments when one type is used for many args	Clifford Wolf	2013-11-19	1	-3/+10
*	Fixed parsing of "parameter integer"	Clifford Wolf	2013-11-13	1	-2/+2
*	Various fixes for correct parameter support	Clifford Wolf	2013-11-07	1	-26/+52
*	Fixed handling of boolean attributes (frontends)	Clifford Wolf	2013-10-24	1	-2/+2
*	Fixed handling of boolean attributes (kernel)	Clifford Wolf	2013-10-24	1	-1/+1
*	fixed Verilog parser filename and line numbering issue with include files	Johann Glaser	2013-08-21	1	-0/+2