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* Fix handling of z_digit "?" and fix optimization of cmp with "z"Clifford Wolf2019-09-131-5/+1
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Fix lexing of integer literals without radixClifford Wolf2019-09-131-1/+1
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Fix lexing of integer literals, fixes #1364Clifford Wolf2019-09-122-3/+3
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* substr() -> compare()Eddie Hung2019-08-071-4/+4
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* RTLIL::S{0,1} -> State::S{0,1}Eddie Hung2019-08-071-12/+12
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* verilog_lexer: Increase YY_BUF_SIZE to 65536David Shah2019-07-261-0/+3
| | | | Signed-off-by: David Shah <dave@ds0.me>
* Merge pull request #1147 from YosysHQ/clifford/fix1144Clifford Wolf2019-07-031-81/+14
|\ | | | | Improve specify dummy parser
| * Some cleanups in "ignore specify parser"Clifford Wolf2019-07-031-79/+5
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * Improve specify dummy parser, fixes #1144Clifford Wolf2019-06-281-2/+9
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | Fix read_verilog assert/assume/etc on default case label, fixes ↵Clifford Wolf2019-07-021-0/+2
|/ | | | | | YosysHQ/SymbiYosys#53 Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Fix segfault on failed VERILOG_FRONTEND::const2ast, closes #1131Clifford Wolf2019-06-261-1/+1
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Merge pull request #1119 from YosysHQ/eddie/fix1118Clifford Wolf2019-06-211-0/+1
|\ | | | | Make genvar a signed type
| * Make genvar a signed typeEddie Hung2019-06-201-0/+1
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* | Maintain "is_unsized" state of constantsEddie Hung2019-06-201-6/+6
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* Merge branch 'unpacked_arrays' of https://github.com/towoe/yosys-sv into ↵Clifford Wolf2019-06-201-1/+7
|\ | | | | | | towoe-unpacked_arrays
| * Unpacked array declaration using sizeTobias Wölfel2019-06-191-1/+7
| | | | | | | | | | | | | | | | Allows fixed-sized array dimension specified by a single number. This commit is based on the work from PeterCrozier https://github.com/YosysHQ/yosys/pull/560. But is split out of the original work.
* | Add "read_verilog -pwires" feature, closes #1106Clifford Wolf2019-06-192-3/+15
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | Add defaultvalue attributeClifford Wolf2019-06-191-0/+11
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | Fix handling of "logic" variables with initial valueClifford Wolf2019-06-191-2/+2
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | Fixed brojen $error()/$info/$warning() on non-generate blocksUdi Finkelstein2019-06-112-3/+13
|/ | | | (within always/initial blocks)
* Merge branch 'pr_elab_sys_tasks' of https://github.com/udif/yosys into ↵Clifford Wolf2019-06-072-1/+15
|\ | | | | | | clifford/pr983
| * Initial implementation of elaboration system tasksUdi Finkelstein2019-05-032-1/+15
| | | | | | | | | | | | | | (IEEE1800-2017 section 20.11) This PR allows us to use $info/$warning/$error/$fatal **at elaboration time** within a generate block. This is very useful to stop a synthesis of a parametrized block when an illegal combination of parameters is chosen.
* | Cleanup tux3-implicit_named_connectionClifford Wolf2019-06-071-1/+1
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | Merge branch 'implicit_named_connection' of https://github.com/tux3/yosys ↵Clifford Wolf2019-06-071-1/+10
|\ \ | | | | | | | | | into tux3-implicit_named_connection
| * | SystemVerilog support for implicit named port connectionstux32019-06-061-9/+17
| | | | | | | | | | | | | | | This is the `foo foo(.port1, .port2);` SystemVerilog syntax introduced in IEEE1800-2005.
* | | Fixed memory leak.Maciej Kurc2019-06-051-0/+4
| | | | | | | | | | | | Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
* | | Added support for parsing attributes on port connections.Maciej Kurc2019-05-311-10/+10
|/ / | | | | | | Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
* | Merge branch 'master' into wandworStefan Biereigel2019-05-272-9/+19
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| * | Added support for unsized constants, fixes #1022Miodrag Milanovic2019-05-272-9/+19
| | | | | | | | | | | | Includes work from @sumit0190 and @AaronKel
* | | fix indentation across filesStefan Biereigel2019-05-231-2/+2
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* | | make lexer/parser aware of wand/wor net typesStefan Biereigel2019-05-232-1/+9
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* | Read bigger Verilog files.Kaj Tuomi2019-05-181-1/+1
| | | | | | | | Hit parser limit with 3M gate design. This commit fix it.
* | Merge pull request #1013 from antmicro/parameter_attributesClifford Wolf2019-05-161-2/+2
|\ \ | | | | | | Support for attributes on parameters and localparams for Verilog frontend
| * | Added support for parsing attributes on parameters in Verilog frontent. ↵Maciej Kurc2019-05-161-2/+2
| | | | | | | | | | | | | | | | | | Content of those attributes is ignored. Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
* | | Make the generated *.tab.hh include all the headers needed to define the union.Henner Zeller2019-05-141-1/+9
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* | Merge pull request #946 from YosysHQ/clifford/specifyClifford Wolf2019-05-064-33/+328
|\ \ | | | | | | Add specify parser
| * \ Merge branch 'master' of github.com:YosysHQ/yosys into clifford/specifyClifford Wolf2019-05-062-2/+10
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| * \ \ Merge remote-tracking branch 'origin/master' into clifford/specifyEddie Hung2019-05-031-2/+2
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| * | | Improve $specrule interfaceClifford Wolf2019-04-232-9/+19
| | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * | | Improve $specrule interfaceClifford Wolf2019-04-231-20/+18
| | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * | | Add $specrule cells for $setup/$hold/$skew specify rulesClifford Wolf2019-04-232-2/+78
| | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * | | Rename T_{RISE,FALL}_AVG to T_{RISE,FALL}_TYP to better match verilog std ↵Clifford Wolf2019-04-231-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | nomenclature Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * | | Un-break default specify parserClifford Wolf2019-04-231-0/+1
| | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * | | Add specify parserClifford Wolf2019-04-234-33/+243
| | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | | | verilog_parser: Fix Bison warningBen Widawsky2019-05-051-1/+1
| |_|/ |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | As of Bison 2.6, name-prefix is deprecated. This fixes frontends/verilog/verilog_parser.y:99.1-34: warning: deprecated directive, use ‘%define api.prefix {frontend_verilog_yy}’ [-Wdeprecated] %name-prefix "frontend_verilog_yy" For details: https://www.gnu.org/software/bison/manual/html_node/Multiple-Parsers.html Compile tested only. Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
* | | Merge pull request #988 from YosysHQ/clifford/fix987Clifford Wolf2019-05-042-1/+5
|\ \ \ | | | | | | | | Add approximate support for SV "var" keyword
| * | | Add approximate support for SV "var" keyword, fixes #987Clifford Wolf2019-05-042-1/+5
| | |/ | |/| | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* / | Add support for SVA "final" keywordClifford Wolf2019-05-042-1/+5
|/ / | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* / Include filename in "Executing Verilog-2005 frontend" message, fixes #959Clifford Wolf2019-04-301-2/+2
|/ | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* New behavior for front-end handling of whiteboxesClifford Wolf2019-04-203-16/+30
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
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