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* | Merge pull request #2005 from YosysHQ/claire/fix1990Claire Wolf2020-05-071-2/+2
|\ \ | | | | | | Add "nowrshmsk" attribute, fix shift-and-mask bit slice write for signed offset
| * | Add AST_SELFSZ and improve handling of bit slicesClaire Wolf2020-05-021-2/+2
| | | | | | | | | | | | Signed-off-by: Claire Wolf <claire@symbioticeda.com>
* | | Merge pull request #2028 from zachjs/masterEddie Hung2020-05-061-1/+6
|\ \ \ | |_|/ |/| | verilog: allow null gen-if then block
| * | verilog: allow null gen-if then blockZachary Snow2020-05-061-1/+6
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* | Merge pull request #2025 from YosysHQ/eddie/frontend_cleanupEddie Hung2020-05-053-15/+15
|\ \ | | | | | | frontend: cleanup to use more ID::*, more dict<> instead of map<>
| * | frontend: cleanup to use more ID::*, more dict<> instead of map<>Eddie Hung2020-05-043-15/+15
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* | Merge pull request #2024 from YosysHQ/eddie/primitive_srcEddie Hung2020-05-051-1/+3
|\ \ | | | | | | verilog: set src attribute for primitives
| * | verilog: set src attribute for primitivesEddie Hung2020-05-041-1/+3
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* / verilog: fix specify src attributeEddie Hung2020-05-041-18/+20
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* Set Verilog source location for explicit blocks (`begin` ... `end`).Alberto Gonzalez2020-04-171-0/+1
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* Add Verilog source location information to `AST_POSEDGE` and `AST_NEGEDGE` ↵Alberto Gonzalez2020-04-171-0/+2
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* Add location information to `AST_CONSTANT` nodes.Alberto Gonzalez2020-04-161-0/+3
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* Merge pull request #1879 from jjj11x/jjj11x/package_declwhitequark2020-04-141-1/+2
|\ | | | | support using previously declared types/localparams/parameters in package
| * support using previously declared types/localparams/params in packageJeff Wang2020-04-071-1/+2
| | | | | | | | | | | | | | (parameters in systemverilog packages can't actually be overridden, so allowing parameters in addition to localparams doesn't actually add any new functionality, but it's useful to be able to use the parameter keyword also)
* | verilog: Fix write to deleted objectDavid Shah2020-04-121-1/+0
|/ | | | Signed-off-by: David Shah <dave@ds0.me>
* Merge pull request #1767 from YosysHQ/eddie/idstringsEddie Hung2020-04-021-27/+27
|\ | | | | IdString: use more ID::*, make them easier to use, speed up IdString::in()
| * kernel: big fat patch to use more ID::*, otherwise ID(*)Eddie Hung2020-04-021-5/+5
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| * kernel: use more ID::*Eddie Hung2020-04-021-22/+22
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* | Merge pull request #1846 from dh73/ast_feClaire Wolf2020-04-021-0/+3
|\ \ | |/ |/| Adding error message for when size (width) of number literal is zero
| * Replacing log_error for log_file_error due consistencyDiego H2020-03-311-2/+1
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| * Adding error message for when size (width) of number literal is zeroDiego H2020-03-301-0/+4
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* | verilog: Add location info for generate constructsDavid Shah2020-04-011-0/+6
|/ | | | Signed-off-by: David Shah <dave@ds0.me>
* Merge pull request #1811 from PeterCrozier/typedef_scopeN. Engelhardt2020-03-304-41/+81
|\ | | | | Support module/package/interface/block scope for typedef names.
| * Inline productions to follow house style.Peter Crozier2020-03-271-33/+29
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| * Error duplicate declarations of a typedef name in the same scope.Peter Crozier2020-03-242-3/+11
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| * Support module/package/interface/block scope for typedef names.Peter Crozier2020-03-234-20/+56
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* | Add support for SystemVerilog-style `define to Verilog frontendRupert Swarbrick2020-03-274-149/+578
|/ | | | | | | | | | | | | | | | | | | | | | | | | | | This patch should support things like `define foo(a, b = 3, c) a+b+c `foo(1, ,2) which will evaluate to 1+3+2. It also spots mistakes like `foo(1) (the 3rd argument doesn't have a default value, so a call site is required to set it). Most of the patch is a simple parser for the format in preproc.cc, but I've also taken the opportunity to wrap up the "name -> definition" map in a type, rather than use multiple std::map's. Since this type needs to be visible to code that touches defines, I've pulled it (and the frontend_verilog_preproc declaration) out into a new file at frontends/verilog/preproc.h and included that where necessary. Finally, the patch adds a few tests in tests/various to check that we are parsing everything correctly.
* Build pkg_user_types before parsing in case of changes in the design.Peter Crozier2020-03-221-6/+3
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* Clear pkg_user_types if no packages following a 'design -reset-vlog'.Peter2020-03-222-0/+5
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* Parser changes to support typedef.Peter2020-03-224-10/+88
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* Merge pull request #1787 from YosysHQ/mmicko/lexer_depsMiodrag Milanović2020-03-191-1/+1
|\ | | | | Add dependency to verilog_lexer.cc
| * Add one mode dependencyMiodrag Milanovic2020-03-191-1/+1
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* | Merge pull request #1775 from huaixv/asserts_locationsN. Engelhardt2020-03-191-7/+30
|\ \ | |/ |/| Add precise locations for asserts
| * Add precise locations for assertshuaixv2020-03-191-7/+30
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* | Add AST node source location information in a couple more parser rules.Alberto Gonzalez2020-03-171-0/+2
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* Merge pull request #1759 from zeldin/constant_with_comment_reduxMiodrag Milanović2020-03-142-19/+43
|\ | | | | refixed parsing of constant with comment between size and value
| * refixed parsing of constant with comment between size and valueMarcus Comstedt2020-03-112-19/+43
| | | | | | | | | | | | The three parts of a based constant (size, base, digits) are now three separate tokens, allowing the linear whitespace (including comments) between them to be treated as normal inter-token whitespace.
* | verilog: also set location for simple_behavioral_stmtEddie Hung2020-03-101-0/+4
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* | Set AST source locations in more parser rules.Alberto Gonzalez2020-03-101-2/+49
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* Fix partsel expr bit width handling and add test caseClaire Wolf2020-03-081-4/+6
| | | | Signed-off-by: Claire Wolf <claire@symbioticeda.com>
* Fix bison warning for "pure-parser" optionClaire Wolf2020-03-031-1/+1
| | | | Signed-off-by: Claire Wolf <claire@symbioticeda.com>
* Closes #1717. Add more precise Verilog source location information to AST ↵Alberto Gonzalez2020-02-234-32/+131
| | | | and RTLIL nodes.
* Merge pull request #1703 from YosysHQ/eddie/specify_improveEddie Hung2020-02-212-29/+81
|\ | | | | Improve specify parser
| * verilog: add support for more delays than just rise/fallEddie Hung2020-02-191-1/+40
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| * verilog: ignore ranges too without -specifyEddie Hung2020-02-131-1/+2
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| * verilog: improve specify support when not in -specify modeEddie Hung2020-02-131-13/+7
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| * verilog: ignore '&&&' when not in -specify modeEddie Hung2020-02-132-5/+6
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| * specify: system timing checks to accept min:typ:max tripleEddie Hung2020-02-131-12/+29
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* | Merge pull request #1642 from jjj11x/jjj11x/sv-enumClaire Wolf2020-02-201-2/+104
|\ \ | |/ |/| Enum support
| * add attributes for enumerated values in ilangJeff Wang2020-02-171-1/+8
| | | | | | | | | | | | - information also useful for strongly-typed enums (not implemented) - resolves enum values in ilang part of #1594 - still need to output enums to VCD (or better yet FST) files
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