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frontends
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verilog
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const2ast.cc
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Author
Age
Files
Lines
*
Fixing old e-mail addresses and deadnames
Claire Xenia Wolf
2021-06-08
1
-1
/
+1
*
Replacing log_error for log_file_error due consistency
Diego H
2020-03-31
1
-2
/
+1
*
Adding error message for when size (width) of number literal is zero
Diego H
2020-03-30
1
-0
/
+4
*
Fix handling of z_digit "?" and fix optimization of cmp with "z"
Clifford Wolf
2019-09-13
1
-5
/
+1
*
Fix lexing of integer literals, fixes #1364
Clifford Wolf
2019-09-12
1
-2
/
+2
*
RTLIL::S{0,1} -> State::S{0,1}
Eddie Hung
2019-08-07
1
-12
/
+12
*
Fix segfault on failed VERILOG_FRONTEND::const2ast, closes #1131
Clifford Wolf
2019-06-26
1
-1
/
+1
*
Maintain "is_unsized" state of constants
Eddie Hung
2019-06-20
1
-6
/
+6
*
Added support for unsized constants, fixes #1022
Miodrag Milanovic
2019-05-27
1
-8
/
+18
*
Convert more log_error() to log_file_error() where possible.
Henner Zeller
2018-07-20
1
-5
/
+3
*
Fixed segfault on invalid verilog constant 1'b_
Clifford Wolf
2015-09-22
1
-1
/
+1
*
Small corrections to const2ast warning messages
Clifford Wolf
2015-08-17
1
-2
/
+2
*
Check base-n literals only contain valid digits
Florian Zeitz
2015-08-17
1
-0
/
+3
*
Warn on literals exceeding the specified bit width
Florian Zeitz
2015-08-17
1
-34
/
+39
*
Another block of spelling fixes
Larry Doolittle
2015-08-14
1
-1
/
+1
*
Fixed handling of [a-fxz?] in decimal constants
Clifford Wolf
2015-08-11
1
-2
/
+7
*
Fixed trailing whitespaces
Clifford Wolf
2015-07-02
1
-2
/
+2
*
Fixed two minor bugs in constant parsing
Clifford Wolf
2014-11-24
1
-1
/
+5
*
Added warning for use of 'z' constants in HDL
Clifford Wolf
2014-11-14
1
-1
/
+9
*
Moved some stuff to kernel/yosys.{h,cc}, using Yosys:: namespace
Clifford Wolf
2014-07-31
1
-0
/
+4
*
Using log_assert() instead of assert()
Clifford Wolf
2014-07-28
1
-2
/
+1
*
Improved parsing of large integer constants
Clifford Wolf
2014-06-15
1
-11
/
+28
*
Fixed handling of unsized constants in verilog frontend
Clifford Wolf
2014-01-24
1
-2
/
+2
*
Major redesign of expr width/sign detecion (verilog/ast frontend)
Clifford Wolf
2013-07-09
1
-1
/
+1
*
Added SAT generator and simple sat_solve command
Clifford Wolf
2013-06-07
1
-3
/
+2
*
initial import
Clifford Wolf
2013-01-05
1
-0
/
+197