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| author | Diego H <diego@symbioticeda.com> | 2020-03-30 17:18:13 -0600 |
|---|---|---|
| committer | Diego H <diego@symbioticeda.com> | 2020-03-30 17:18:13 -0600 |
| commit | 92809bb1d3c225ab0c846a55979f6914dcfbd886 (patch) | |
| tree | d2f60653faed30758dfcf62de05a029652106f11 /frontends/verilog/const2ast.cc | |
| parent | 05f74d4f315eab0fa0c7e83627482f5160113ba5 (diff) | |
| download | yosys-92809bb1d3c225ab0c846a55979f6914dcfbd886.tar.gz yosys-92809bb1d3c225ab0c846a55979f6914dcfbd886.tar.bz2 yosys-92809bb1d3c225ab0c846a55979f6914dcfbd886.zip | |
Adding error message for when size (width) of number literal is zero
Diffstat (limited to 'frontends/verilog/const2ast.cc')
| -rw-r--r-- | frontends/verilog/const2ast.cc | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/frontends/verilog/const2ast.cc b/frontends/verilog/const2ast.cc index 49281f7e7..25d257867 100644 --- a/frontends/verilog/const2ast.cc +++ b/frontends/verilog/const2ast.cc @@ -139,6 +139,10 @@ static void my_strtobin(std::vector<RTLIL::State> &data, const char *str, int le data.resize(len_in_bits, msb); } + if (len_in_bits == 0) + log_error("Illegal integer constant size of zero in %s:%d (IEEE 1800-2012, 5.7).\n", + current_filename.c_str(), get_line_num()); + if (len > len_in_bits) log_warning("Literal has a width of %d bit, but value requires %d bit. (%s:%d)\n", len_in_bits, len, current_filename.c_str(), get_line_num()); |