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* Add ability to override verilog mode for verific -f commandMiodrag Milanovic2022-02-091-2/+44
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* Use bmux for NTO1MUXMiodrag Milanovic2022-02-021-16/+2
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* Add YOSYS to the implicitly defined verilog macros in verificClaire Xenia Wolf2021-12-131-1/+2
| | | | Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
* Merge pull request #3102 from YosysHQ/claire/enumxzMiodrag Milanović2021-12-101-1/+1
|\ | | | | Fix verific import of enum values with x and/or z
| * Fix verific import of enum values with x and/or zClaire Xenia Wolf2021-12-101-1/+1
| | | | | | | | Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
* | Update verific.ccClaire Xen2021-12-101-4/+7
| | | | | | Ad-hoc fixes/improvements
* | If direction NONE use that from first bitMiodrag Milanovic2021-12-081-0/+7
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* Make sure cell names are unique for wide operatorsMiodrag Milanovic2021-12-031-2/+2
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* No need to alocate more memory than usedMiodrag Milanovic2021-11-101-1/+0
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* Add "verific -cfg" commandClaire Xenia Wolf2021-11-011-2/+75
| | | | Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
* Fix verific gclk handling for async-load FFsClaire Xenia Wolf2021-10-311-12/+67
| | | | Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
* Enable async load dff emit by default in VerificMiodrag Milanovic2021-10-271-1/+1
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* Revert "Compile option for enabling async load verific support"Miodrag Milanovic2021-10-271-4/+1
| | | | This reverts commit b8624ad2aef941776f5b4a08f66f8d43e70f8467.
* Compile option for enabling async load verific supportMiodrag Milanovic2021-10-251-1/+4
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* Fix verific.cc PRIM_DLATCH handlingClaire Xenia Wolf2021-10-211-1/+7
| | | | Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
* Initial Verific impoter support for {PRIM,WIDE_OPER}_DLATCH{,RS}Claire Xenia Wolf2021-10-211-4/+55
| | | | Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
* Option to disable verific VHDL supportMiodrag Milanovic2021-10-202-11/+45
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* Support PRIM_BUFIF1 primitiveMiodrag Milanovic2021-10-141-2/+2
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* Merge pull request #3039 from YosysHQ/claire/verific_aldffClaire Xen2021-10-112-1/+91
|\ | | | | Add support for $aldff flip-flops to verific importer
| * Add Verific adffe/dffsre/aldffe FIXMEsClaire Xenia Wolf2021-10-111-0/+3
| | | | | | | | Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
| * Fixes and add comments for open FIXME itemsClaire Xenia Wolf2021-10-081-1/+34
| | | | | | | | Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
| * Add support for $aldff flip-flops to verific importerClaire Xenia Wolf2021-10-082-1/+55
| | | | | | | | Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
* | Import module attributes from VerificMiodrag Milanovic2021-10-101-0/+1
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* verific set db_infer_set_reset_registersMiodrag Milanovic2021-10-041-0/+1
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* update required verific versionMiodrag Milanovic2021-09-021-1/+1
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* Make Verific extensions optionalMiodrag Milanovic2021-08-201-1/+6
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* Require latest verificMiodrag Milanovic2021-08-021-1/+1
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* Update to latest verificMiodrag Milanovic2021-07-211-3/+3
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* Update to latest Verific with extensions for initial assertionsMiodrag Milanovic2021-07-091-14/+9
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* Add additional helpMiodrag Milanovic2021-07-051-0/+22
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* Support command files in VerificMiodrag Milanovic2021-06-161-0/+39
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* Fixing old e-mail addresses and deadnamesClaire Xenia Wolf2021-06-083-3/+3
| | | | | | | | s/((Claire|Xen|Xenia|Clifford)\s+)+(Wolf|Xen)\s+<(claire|clifford)@(symbioticeda.com|clifford.at|yosyshq.com)>/Claire Xenia Wolf <claire@yosyshq.com>/gi; s/((Nina|Nak|N\.)\s+)+Engelhardt\s+<nak@(symbioticeda.com|yosyshq.com)>/N. Engelhardt <nak@yosyshq.com>/gi; s/((David)\s+)+Shah\s+<(dave|david)@(symbioticeda.com|yosyshq.com|ds0.me)>/David Shah <dave@ds0.me>/gi; s/((Miodrag)\s+)+Milanovic\s+<(miodrag|micko)@(symbioticeda.com|yosyshq.com)>/Miodrag Milanovic <micko@yosyshq.com>/gi; s,https?://www.clifford.at/yosys/,http://yosyshq.net/yosys/,g;
* Update READMEClaire Xen2021-03-041-4/+4
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* Merge pull request #2574 from dh73/masterClaire Xen2021-02-151-0/+5
|\ | | | | Accept disable case for SVA liveness properties.
| * Accept disable case for SVA liveness properties.Diego H2021-02-041-0/+5
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* | Ganulate Verific supportMiodrag Milanovic2021-02-121-8/+16
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* Require latest Verific buildMiodrag Milanovic2021-01-301-1/+1
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* Switch verific bindings from Symbiotic EDA flavored Verific to YosysHQ ↵Claire Xenia Wolf2021-01-201-18/+18
| | | | | | flavored Verific Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
* Bump required Verific versionMiodrag Milanovic2020-12-021-1/+1
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* Update verific versionMiodrag Milanovic2020-10-301-1/+1
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* extend verific library API for formal apps and generatorsMiodrag Milanovic2020-10-121-15/+83
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* Update required Verific versionMiodrag Milanović2020-10-051-1/+1
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* use sha1 for parameter list in case if they contain spacesMiodrag Milanovic2020-09-301-2/+18
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* Better error for unsupported SVA sequenceMiodrag Milanovic2020-09-181-2/+8
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* Use latest verificMiodrag Milanovic2020-09-021-1/+1
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* Reorder to prevent crashMiodrag Milanovic2020-08-311-3/+3
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* ast recognize lower case x and z and verific gives upper caseMiodrag Milanovic2020-08-301-2/+6
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* Do not check for 1 and 0 onlyMiodrag Milanovic2020-08-301-6/+0
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* Fix import of VHDL enumsMiodrag Milanovic2020-08-301-11/+22
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* Add formal apps and template generatorsMiodrag Milanovic2020-08-261-1/+223
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