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| author | Claire Xen <claire@clairexen.net> | 2021-02-15 17:49:11 +0100 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2021-02-15 17:49:11 +0100 |
| commit | 27d77415408be5e61c6334655d2f82693d20af44 (patch) | |
| tree | 4ef45507ecd781268ecbc3b96ff0cfa79c2d2892 /frontends/verific | |
| parent | 4e741adda976260f620e5787d6db3cb28e0e35e7 (diff) | |
| parent | c96eb2fbd7cb2f4838350c02baf3e4b23c4b2ad2 (diff) | |
| download | yosys-27d77415408be5e61c6334655d2f82693d20af44.tar.gz yosys-27d77415408be5e61c6334655d2f82693d20af44.tar.bz2 yosys-27d77415408be5e61c6334655d2f82693d20af44.zip | |
Merge pull request #2574 from dh73/master
Accept disable case for SVA liveness properties.
Diffstat (limited to 'frontends/verific')
| -rw-r--r-- | frontends/verific/verificsva.cc | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/frontends/verific/verificsva.cc b/frontends/verific/verificsva.cc index 632043b6f..1f5da1b1d 100644 --- a/frontends/verific/verificsva.cc +++ b/frontends/verific/verificsva.cc @@ -1759,6 +1759,11 @@ struct VerificSvaImporter clocking.addDff(NEW_ID, sig_en, sig_en_q, State::S0); } + // accept in disable case + + if (clocking.disable_sig != State::S0) + sig_a_q = module->Or(NEW_ID, sig_a_q, clocking.disable_sig); + // generate fair/live cell RTLIL::Cell *c = nullptr; |