iCE40/yosys - [no description]

	Commit message (Expand)	Author	Age	Files	Lines
*	Add support for verific mem initialization	Clifford Wolf	2017-02-11	1	-0/+38
*	Fix another stupid bug in the same line	Clifford Wolf	2017-02-11	1	-1/+1
*	Add verific support for initialized variables	Clifford Wolf	2017-02-11	1	-3/+47
*	Improve handling of Verific warnings and error messages	Clifford Wolf	2017-02-11	1	-4/+10
*	Fix extremely stupid typo	Clifford Wolf	2017-02-11	1	-1/+1
*	Add "rand" and "rand const" verific support	Clifford Wolf	2017-02-09	1	-0/+41
*	Add PSL parser mode to verific front-end	Clifford Wolf	2017-02-08	1	-2/+17
*	Add $cover cell type and SVA cover() support	Clifford Wolf	2017-02-04	1	-2/+2
*	Add assert/assume support to verific front-end	Clifford Wolf	2017-02-04	2	-625/+687
*	Added "yosys -D" feature	Clifford Wolf	2016-04-21	1	-1/+1
*	Support for more Verific primitives (patch I got per email)	Clifford Wolf	2016-02-13	1	-1/+31
*	Bugfix in Verific front-end	Clifford Wolf	2016-02-03	1	-2/+5
*	Updated verific build instructions	Clifford Wolf	2016-02-02	1	-2/+0
*	Added addBufGate module method	Clifford Wolf	2016-02-02	1	-0/+5
*	Added PRIM_DLATCHRS support to verific front-end	Clifford Wolf	2015-11-24	1	-0/+10
*	Fixed performance bug in Verific importer	Clifford Wolf	2015-11-16	1	-10/+12
*	Changes for Verific 3.16_484_32_151112	Clifford Wolf	2015-11-12	2	-3/+6
*	Import more std:: stuff into Yosys namespace	Clifford Wolf	2015-10-25	1	-5/+5
*	Added read-enable to memory model	Clifford Wolf	2015-09-25	1	-1/+2
*	Spell check (by Larry Doolittle)	Clifford Wolf	2015-08-14	1	-1/+1
*	Fixed trailing whitespaces	Clifford Wolf	2015-07-02	1	-3/+3
*	Verific build fixes	Clifford Wolf	2015-05-17	2	-2/+2
*	Added log_warning() API	Clifford Wolf	2014-11-09	1	-1/+1
*	Added "ENABLE_PLUGINS := 0" to verific amd64 build instructions	Clifford Wolf	2014-11-08	1	-0/+1
*	Header changes so it will compile on VS	William Speirs	2014-10-17	1	-2/+5
*	Renamed SIZE() to GetSize() because of name collision on Win32	Clifford Wolf	2014-10-10	1	-8/+8
*	Corrected spelling mistakes found by lintian	Ruben Undheim	2014-09-06	2	-2/+2
*	Added module->uniquify()	Clifford Wolf	2014-08-16	1	-6/+2
*	Renamed $_INV_ cell type to $_NOT_	Clifford Wolf	2014-08-15	1	-3/+3
*	Fixed building verific bindings	Clifford Wolf	2014-08-12	2	-3/+3
*	Fixed build of verific bindings	Clifford Wolf	2014-07-31	1	-11/+11
*	Added module->design and cell->module, wire->module pointers	Clifford Wolf	2014-07-31	1	-2/+2
*	Moved some stuff to kernel/yosys.{h,cc}, using Yosys:: namespace	Clifford Wolf	2014-07-31	1	-1/+7
*	Using log_assert() instead of assert()	Clifford Wolf	2014-07-28	1	-1/+0
*	Fixed verific bindings for new RTLIL api	Clifford Wolf	2014-07-27	2	-55/+42
*	Updated verific build/test instructions	Clifford Wolf	2014-07-25	2	-13/+11
*	Various fixes in Verific frontend for new RTLIL API	Clifford Wolf	2014-07-23	2	-27/+55
*	Fixed mapping of Verific WIDE_DFFRS operator	Clifford Wolf	2014-03-20	1	-2/+2
*	Fixed mapping of Verific FADD primitive with unconnected outputs	Clifford Wolf	2014-03-20	1	-4/+5
*	Progress in Verific bindings	Clifford Wolf	2014-03-17	1	-8/+51
*	Progress in Verific bindings	Clifford Wolf	2014-03-17	1	-5/+50
*	Progress in Verific bindings	Clifford Wolf	2014-03-17	1	-0/+2
*	Added support for memories to verific bindings	Clifford Wolf	2014-03-16	2	-1/+86
*	Use Verific Net::{IsGnd,IsPwr} API in Verific bindings	Clifford Wolf	2014-03-16	1	-27/+11
*	Progress in Verific bindings	Clifford Wolf	2014-03-15	1	-39/+16
*	Progress in Verific bindings	Clifford Wolf	2014-03-15	1	-7/+15
*	Progress in Verific bindings	Clifford Wolf	2014-03-15	1	-31/+31
*	Progress in Verific bindings	Clifford Wolf	2014-03-14	1	-13/+38
*	Progress in Verific bindings	Clifford Wolf	2014-03-14	1	-222/+338
*	Progress in Verific bindings	Clifford Wolf	2014-03-13	1	-10/+65