iCE40/yosys - [no description]

	Commit message (Expand)	Author	Age	Files	Lines
*	Refactoring: Renamed RTLIL::Module::cells to cells_	Clifford Wolf	2014-07-27	1	-2/+2
*	Refactoring: Renamed RTLIL::Module::wires to wires_	Clifford Wolf	2014-07-27	1	-3/+3
*	Changed users of cell->connections_ to the new API (sed command)	Clifford Wolf	2014-07-26	1	-62/+62
*	Renamed RTLIL::{Module,Cell}::connections to connections_	Clifford Wolf	2014-07-26	1	-62/+62
*	Use only module->addCell() and module->remove() to create and delete cells	Clifford Wolf	2014-07-25	1	-55/+14
*	SigSpec refactoring: using the accessor functions everywhere	Clifford Wolf	2014-07-22	1	-8/+8
*	SigSpec refactoring: renamed chunks and width to __chunks and __width	Clifford Wolf	2014-07-22	1	-8/+8
*	Replaced depricated NEW_WIRE macro with module->addWire() calls	Clifford Wolf	2014-07-21	1	-10/+10
*	Removed deprecated module->new_wire()	Clifford Wolf	2014-07-21	1	-5/+5
*	Added "inout" ports support to read_liberty	Clifford Wolf	2014-07-16	1	-1/+6
*	Set blackbox attribute in "read_liberty -lib"	Clifford Wolf	2014-07-16	1	-0/+3
*	Fixed spelling of "direction" in read_liberty messages	Clifford Wolf	2014-07-16	1	-2/+2
*	new flags -ignore_miss_func and -ignore_miss_dir for read_liberty	Johann Glaser	2014-05-28	1	-4/+40
*	Added ff and latch support to read_liberty	Clifford Wolf	2014-02-15	1	-40/+254
*	Bugfix in expression parser of read_liberty	Clifford Wolf	2014-02-15	1	-2/+1
*	Added liberty frontend	Clifford Wolf	2014-02-15	1	-0/+359