iCE40/yosys - [no description]

	Commit message (Expand)	Author	Age	Files	Lines
*	Refactoring: Renamed RTLIL::Module::cells to cells_	Clifford Wolf	2014-07-27	1	-2/+2
*	Refactoring: Renamed RTLIL::Module::wires to wires_	Clifford Wolf	2014-07-27	2	-8/+8
*	Changed a lot of code to the new RTLIL::Wire constructors	Clifford Wolf	2014-07-26	2	-16/+11
*	Added RTLIL::Cell::has(portname)	Clifford Wolf	2014-07-26	1	-1/+1
*	Manual fixes for new cell connections API	Clifford Wolf	2014-07-26	2	-3/+3
*	Changed users of cell->connections_ to the new API (sed command)	Clifford Wolf	2014-07-26	3	-88/+88
*	Renamed RTLIL::{Module,Cell}::connections to connections_	Clifford Wolf	2014-07-26	3	-89/+89
*	Use only module->addCell() and module->remove() to create and delete cells	Clifford Wolf	2014-07-25	3	-113/+34
*	Fixed two memory leaks in ast simplify	Clifford Wolf	2014-07-25	1	-1/+6
*	Updated verific build/test instructions	Clifford Wolf	2014-07-25	2	-13/+11
*	Replaced more old SigChunk programming patterns	Clifford Wolf	2014-07-24	1	-7/+7
*	Added "make PRETTY=1"	Clifford Wolf	2014-07-24	2	-6/+6
*	Various fixes in Verific frontend for new RTLIL API	Clifford Wolf	2014-07-23	2	-27/+55
*	Various small fixes (from gcc compiler warnings)	Clifford Wolf	2014-07-23	1	-1/+1
*	Removed RTLIL::SigSpec::optimize()	Clifford Wolf	2014-07-23	1	-11/+0
*	Refactoring {SigSpec\|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 3/3	Clifford Wolf	2014-07-23	1	-2/+2
*	Refactoring {SigSpec\|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 2/3	Clifford Wolf	2014-07-23	1	-2/+2
*	SigSpec refactoring: More cleanups of old SigSpec use pattern	Clifford Wolf	2014-07-22	1	-3/+6
*	SigSpec refactoring: change RTLIL::SigSpec::chunks() to be read-only, created...	Clifford Wolf	2014-07-22	1	-1/+1
*	SigSpec refactoring: change RTLIL::SigSpec::size() to be read-only	Clifford Wolf	2014-07-22	2	-92/+17
*	SigSpec refactoring: using the accessor functions everywhere	Clifford Wolf	2014-07-22	3	-82/+82
*	SigSpec refactoring: renamed chunks and width to __chunks and __width	Clifford Wolf	2014-07-22	3	-82/+82
*	Fixed ilang parsing of process attributes	Clifford Wolf	2014-07-22	1	-0/+1
*	Fixed make rules for ilang parser	Clifford Wolf	2014-07-22	1	-1/+3
*	Added "autoidx" statement to ilang file format	Clifford Wolf	2014-07-21	2	-25/+10
*	Replaced depricated NEW_WIRE macro with module->addWire() calls	Clifford Wolf	2014-07-21	1	-10/+10
*	Removed deprecated module->new_wire()	Clifford Wolf	2014-07-21	1	-5/+5
*	Implemented dynamic bit-/part-select for memory writes	Clifford Wolf	2014-07-17	1	-2/+26
*	Added support for bit/part select to mem2reg rewriter	Clifford Wolf	2014-07-17	1	-0/+9
*	Added support for constant bit- or part-select for memory writes	Clifford Wolf	2014-07-17	1	-9/+36
*	Added "inout" ports support to read_liberty	Clifford Wolf	2014-07-16	1	-1/+6
*	Set blackbox attribute in "read_liberty -lib"	Clifford Wolf	2014-07-16	1	-0/+3
*	Fixed spelling of "direction" in read_liberty messages	Clifford Wolf	2014-07-16	1	-2/+2
*	changes in verilog frontend for new $mem/$memwr WR_EN interface	Clifford Wolf	2014-07-16	2	-7/+6
*	Added passing of various options to vhdl2verilog	Clifford Wolf	2014-07-12	1	-5/+36
*	Fixed processing of initial values for block-local variables	Clifford Wolf	2014-07-11	1	-0/+5
*	fixed parsing of constant with comment between size and value	Clifford Wolf	2014-07-02	1	-0/+7
*	Fixed handling of mixed real/int ternary expressions	Clifford Wolf	2014-06-25	1	-0/+16
*	More found_real-related fixes to AstNode::detectSignWidthWorker	Clifford Wolf	2014-06-24	1	-6/+6
*	fixed signdness detection for expressions with reals	Clifford Wolf	2014-06-21	1	-2/+8
*	Added AstNode::MEM2REG_FL_CMPLX_LHS	Clifford Wolf	2014-06-17	2	-0/+23
*	Improved handling of relational op of real values	Clifford Wolf	2014-06-17	1	-8/+9
*	Improved ternary support for real values	Clifford Wolf	2014-06-16	1	-13/+24
*	Use undef (x/z vs. NaN) rules for real values from IEEE Std 1800-2012	Clifford Wolf	2014-06-16	2	-0/+11
*	Fixed parsing of TOK_INTEGER (implies TOK_SIGNED)	Clifford Wolf	2014-06-16	1	-5/+11
*	Added found_real feature to AstNode::detectSignWidth	Clifford Wolf	2014-06-16	2	-6/+11
*	Improved AstNode::realAsConst for large numbers	Clifford Wolf	2014-06-15	1	-1/+1
*	Improved parsing of large integer constants	Clifford Wolf	2014-06-15	1	-11/+28
*	Improved AstNode::asReal for large integers	Clifford Wolf	2014-06-15	2	-10/+13
*	improved (fixed) conversion of real values to bit vectors	Clifford Wolf	2014-06-14	4	-11/+30