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* genrtlil: emit \src attribute on CaseRule.whitequark2019-07-081-0/+1
* Add "read_verilog -pwires" feature, closes #1106Clifford Wolf2019-06-193-6/+29
* Fixes and cleanups in AST_TECALL handlingClifford Wolf2019-06-073-46/+34
* Merge branch 'pr_elab_sys_tasks' of https://github.com/udif/yosys into cliffo...Clifford Wolf2019-06-074-4/+49
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| * Initial implementation of elaboration system tasksUdi Finkelstein2019-05-034-4/+49
* | Merge branch 'master' into wandworStefan Biereigel2019-05-273-5/+28
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| * \ Merge pull request #1044 from mmicko/invalid_width_rangeClifford Wolf2019-05-271-1/+2
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| | * | Give error instead of asserting for invalid range, fixes #947Miodrag Milanovic2019-05-271-1/+2
| * | | Added support for unsized constants, fixes #1022Miodrag Milanovic2019-05-273-4/+26
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* | | remove leftovers from ast data structuresStefan Biereigel2019-05-272-4/+0
* | | move wand/wor resolution into hierarchy passStefan Biereigel2019-05-271-97/+14
* | | fix assignment of non-wiresStefan Biereigel2019-05-231-16/+19
* | | fix indentation across filesStefan Biereigel2019-05-233-61/+81
* | | implementation for assignments workingStefan Biereigel2019-05-233-14/+83
* | | make lexer/parser aware of wand/wor net typesStefan Biereigel2019-05-231-1/+1
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* | Merge pull request #946 from YosysHQ/clifford/specifyClifford Wolf2019-05-062-1/+30
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| * | Improve write_verilog specify supportClifford Wolf2019-05-041-0/+3
| * | Merge remote-tracking branch 'origin/master' into clifford/specifyEddie Hung2019-05-032-0/+12
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| * | | Add $specrule cells for $setup/$hold/$skew specify rulesClifford Wolf2019-04-232-2/+8
| * | | Allow $specify[23] cells in blackbox modulesClifford Wolf2019-04-231-0/+6
| * | | Checking and fixing specify cells in genRTLILClifford Wolf2019-04-231-1/+15
* | | | Merge branch 'master' of github.com:YosysHQ/yosys into clifford/fix968Clifford Wolf2019-05-062-0/+3
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| * | | Add splitcmplxassign test case and silence splitcmplxassign warningClifford Wolf2019-05-011-0/+1
| * | | Fix width detection of memory access with bit slice, fixes #974Clifford Wolf2019-05-011-0/+2
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* / | Re-enable "final loop assignment" featureClifford Wolf2019-05-011-2/+0
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* | Disabled "final loop assignment" featureClifford Wolf2019-04-301-0/+2
* | Add final loop variable assignment when unrolling for-loops, fixes #968Clifford Wolf2019-04-301-0/+7
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* Determine correct signedness and expression width in for loop unrolling, fixe...Clifford Wolf2019-04-221-3/+18
* Merge pull request #909 from zachjs/masterClifford Wolf2019-04-221-1/+20
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| * support repeat loops with constant repeat counts outside of constant functionsZachary Snow2019-04-091-1/+20
* | Add "noblackbox" attributeClifford Wolf2019-04-211-17/+27
* | New behavior for front-end handling of whiteboxesClifford Wolf2019-04-202-18/+70
* | Add "whitebox" attribute, add "read_verilog -wb"Clifford Wolf2019-04-182-4/+22
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* Fix mem2reg handling of memories with upto data ports, fixes #888Clifford Wolf2019-03-211-1/+10
* Improve "read_verilog -dump_vlog[12]" handling of upto rangesClifford Wolf2019-03-211-3/+6
* Improve read_verilog debug output capabilitiesClifford Wolf2019-03-212-10/+18
* fix local name resolution in prefix constructsZachary Snow2019-03-181-1/+5
* Improve handling of "full_case" attributesClifford Wolf2019-03-141-0/+9
* Improve handling of memories used in mem index expressions on LHS of an assig...Clifford Wolf2019-03-121-5/+16
* Remove outdated "blocking assignment to memory" warningClifford Wolf2019-03-121-10/+0
* Only set MEM2REG_FL_CONST_LHS/MEM2REG_FL_VAR_LHS for non-init writes, fixes #867Clifford Wolf2019-03-121-6/+8
* Merge pull request #858 from YosysHQ/clifford/svalabelsClifford Wolf2019-03-092-3/+10
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| * Add support for SVA labels in read_verilogClifford Wolf2019-03-072-3/+10
* | Fix handling of task output ports in clocked always blocks, fixes #857Clifford Wolf2019-03-071-15/+18
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* Merge pull request #848 from YosysHQ/clifford/fix763Clifford Wolf2019-03-021-1/+5
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| * Fix error for wire decl in always block, fixes #763Clifford Wolf2019-03-021-1/+5
* | Only run derive on blackbox modules when ports have dynamic sizeClifford Wolf2019-03-022-0/+20
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* Fix $global_clock handling vs autowireClifford Wolf2019-03-021-1/+1
* Fix $readmem[hb] for mem2reg memories, fixes #785Clifford Wolf2019-03-021-0/+35
* Use mem2reg on memories that only have constant-index write portsClifford Wolf2019-03-012-0/+13