iCE40/yosys - [no description]

	Commit message (Collapse)	Author	Age	Files	Lines
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*	Added handling of real-valued parameters/localparams	Clifford Wolf	2014-06-14	2	-17/+47
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*	Implemented more real arithmetic	Clifford Wolf	2014-06-14	1	-27/+70
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*	Implemented basic real arithmetic	Clifford Wolf	2014-06-14	3	-6/+51
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*	Added real->int convertion in ast genrtlil	Clifford Wolf	2014-06-14	1	-0/+12
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*	Added Verilog lexer and parser support for real values	Clifford Wolf	2014-06-13	2	-0/+7
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*	Add support for cell arrays	Clifford Wolf	2014-06-07	3	-0/+27
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*	Added support for repeat stmt in const functions	Clifford Wolf	2014-06-07	1	-0/+19
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*	further improved const function support	Clifford Wolf	2014-06-07	3	-17/+22
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*	improved const function support	Clifford Wolf	2014-06-06	3	-5/+41
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*	fix functions with no block (but single statement, loop, etc.)	Clifford Wolf	2014-06-06	1	-11/+4
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*	improved ast simplify of const functions	Clifford Wolf	2014-06-06	1	-7/+28
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*	added while and repeat support to verilog parser	Clifford Wolf	2014-06-06	2	-0/+2
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*	Include id2ast pointers when dumping AST	Clifford Wolf	2014-03-05	1	-0/+6
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*	Fixed merging of compatible wire decls in AST frontend	Clifford Wolf	2014-03-05	1	-1/+4
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*	Bugfix in recursive AST simplification	Clifford Wolf	2014-03-05	1	-10/+22
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*	Fixed bit-extending in $mux argument (use $bu0 instead of $pos)	Clifford Wolf	2014-02-26	1	-5/+5
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*	Don't blow up constants unneccessarily in Verilog frontend	Clifford Wolf	2014-02-24	1	-1/+1
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*	Fixed bug in generation of undefs for $memwr MUXes	Clifford Wolf	2014-02-22	1	-4/+6
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*	Cleanups in handling of read_verilog -defer and -icells	Clifford Wolf	2014-02-20	1	-6/+7
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*	Added Verilog support for "`default_nettype none"	Clifford Wolf	2014-02-17	3	-6/+13
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*	Improved support for constant functions	Clifford Wolf	2014-02-16	1	-1/+50
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*	Correctly convert constants to RTLIL (fixed undef handling)	Clifford Wolf	2014-02-15	1	-11/+1
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*	Be more conservative with new const-function code	Clifford Wolf	2014-02-14	1	-1/+5
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*	Added support for FOR loops in function calls in parameters	Clifford Wolf	2014-02-14	3	-0/+43
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*	Created basic support for function calls in parameter values	Clifford Wolf	2014-02-14	4	-49/+184
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*	Implemented read_verilog -defer	Clifford Wolf	2014-02-13	2	-58/+79
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*	Fixed gcc compiler warnings with release build	Clifford Wolf	2014-02-06	1	-1/+1
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*	Fixed bug in sequential sat proofs and improved handling of asserts	Clifford Wolf	2014-02-04	1	-0/+2
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*	Added TRANSPARENT parameter to $memrd (and RD_TRANSPARENT to $mem)	Clifford Wolf	2014-02-03	1	-0/+1
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*	Added constant size expression support of sized constants	Clifford Wolf	2014-02-01	4	-0/+22
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*	Bugfix in name resolution with generate blocks	Clifford Wolf	2014-01-30	1	-1/+1
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*	Added read_verilog -icells option	Clifford Wolf	2014-01-29	3	-5/+11
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*	Fixed algorithmic complexity of AST simplification of long expressions	Clifford Wolf	2014-01-20	3	-6/+13
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*	Added $assert cell	Clifford Wolf	2014-01-19	2	-0/+92
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*	Added Verilog parser support for asserts	Clifford Wolf	2014-01-19	2	-0/+2
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*	Fixed typo in frontends/ast/simplify.cc	Clifford Wolf	2014-01-12	1	-1/+1
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*	Added correct handling of $memwr priority	Clifford Wolf	2014-01-03	1	-0/+2
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*	Fixed a stupid access after delete bug	Clifford Wolf	2013-12-29	1	-1/+2
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*	Added support for non-const === and !== (for miter circuits)	Clifford Wolf	2013-12-27	1	-2/+2
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*	Added proper === and !== support in constant expressions	Clifford Wolf	2013-12-27	4	-12/+26
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*	Keep strings as strings in const ternary and concat	Clifford Wolf	2013-12-05	3	-5/+25
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*	Added const folding support for $signed and $unsigned	Clifford Wolf	2013-12-05	1	-0/+7
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*	Added AstNode::mkconst_str API	Clifford Wolf	2013-12-05	2	-0/+18
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*	Fixed generate-for (and disabled double warning for auto-wire)	Clifford Wolf	2013-12-04	1	-1/+5
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*	Added support for $clog2 system function	Clifford Wolf	2013-12-04	1	-4/+20
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*	Various improvements in support for generate statements	Clifford Wolf	2013-12-04	4	-2/+91
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*	Replaced signed_parameters API with CONST_FLAG_SIGNED	Clifford Wolf	2013-12-04	3	-7/+3
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*	Replaced RTLIL::Const::str with generic decoder method	Clifford Wolf	2013-12-04	3	-24/+37
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*	Added support for local regs in named blocks	Clifford Wolf	2013-12-04	2	-0/+25
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*	Fixed temp net name generation in rtlil process generator for abbreviated ↵	Clifford Wolf	2013-11-28	1	-0/+2
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