iCE40/yosys - [no description]

	Commit message (Expand)	Author	Age	Files	Lines
...
*	Use proper bit width ans sign extension for const folding	Clifford Wolf	2013-11-04	1	-17/+18
*	Fixes for early width and sign detection in ast simplifier	Clifford Wolf	2013-11-04	1	-1/+2
*	further improved early width and sign detection in ast simplifier	Clifford Wolf	2013-11-04	2	-11/+117
*	Fixed detectSignWidthWorker (ast frontend) for AST_CONCAT	Clifford Wolf	2013-11-03	1	-1/+1
*	Behavior should be identical now to rev. 0b4a64ac6adbd6 (next: testing before...	Clifford Wolf	2013-11-02	2	-2/+6
*	Various ast changes for early expression width detection (prep for constfold ...	Clifford Wolf	2013-11-02	4	-30/+139
*	Fixed handling of boolean attributes (frontends)	Clifford Wolf	2013-10-24	4	-12/+27
*	Added support for notif0/notif1 primitives	Johann Glaser	2013-08-20	1	-3/+7
*	Fixed width and sign detection for ** operator	Clifford Wolf	2013-08-19	1	-3/+3
*	Added support for bufif0/bufif1 primitives	Clifford Wolf	2013-08-19	1	-32/+58
*	Improved ast dumping (ast/verilog frontend)	Clifford Wolf	2013-08-19	3	-52/+24
*	Added support for "2**n" shifter encoding	Clifford Wolf	2013-08-12	1	-0/+4
*	Added $div and $mod technology mapping	Clifford Wolf	2013-08-09	1	-1/+1
*	Added "design" command (-reset, -save, -load)	Clifford Wolf	2013-07-27	2	-0/+16
*	More fixes in ternary op sign handling	Clifford Wolf	2013-07-12	1	-0/+3
*	Fixed sign handling in ternary operator	Clifford Wolf	2013-07-12	1	-2/+2
*	Another vloghammer related bugfix	Clifford Wolf	2013-07-11	1	-1/+1
*	Fixed sign propagation in bit-wise operators	Clifford Wolf	2013-07-09	1	-0/+1
*	More fixes in ast expression sign/width handling	Clifford Wolf	2013-07-09	1	-9/+8
*	Major redesign of expr width/sign detecion (verilog/ast frontend)	Clifford Wolf	2013-07-09	2	-34/+168
*	Fixed another bug found using vloghammer	Clifford Wolf	2013-07-07	1	-1/+1
*	Fixed AST_CONSTANT node generation	Clifford Wolf	2013-07-07	1	-1/+1
*	Added defparam support to Verilog/AST frontend	Clifford Wolf	2013-07-04	4	-3/+22
*	More fixes for bugs found using xsthammer	Clifford Wolf	2013-06-13	1	-4/+2
*	Sign-extension related fixes in SatGen and AST frontend	Clifford Wolf	2013-06-10	1	-0/+2
*	Fixes and improvements in AST const folding	Clifford Wolf	2013-06-10	2	-1/+11
*	Enabled AST/Verilog front-end optimizations per default	Clifford Wolf	2013-06-10	4	-10/+20
*	Added log_assert() api	Clifford Wolf	2013-05-24	1	-2/+1
*	Merge branch 'bugfix'	Clifford Wolf	2013-05-16	1	-2/+0
\|\
\| *	Fixed synthesis of functions in latched blocks	Clifford Wolf	2013-05-16	1	-2/+0
* \|	Fixed handling of positional module parameters	Clifford Wolf	2013-04-26	1	-6/+4
* \|	Only use sha1 checksums for names of parametric modules when the verbose form...	Clifford Wolf	2013-04-26	1	-9/+20
* \|	Fixed a bug in AST frontend for cases with non-blocking assigned variables as...	Clifford Wolf	2013-04-13	1	-4/+4
* \|	Now only use value from "initial" when no matching "always" block is found	Clifford Wolf	2013-03-31	3	-7/+31
* \|	Added AST_INITIAL (before verilog "initial" was mapped to AST_ALWAYS)	Clifford Wolf	2013-03-31	4	-2/+14
* \|	Implemented proper handling of stub placeholder modules	Clifford Wolf	2013-03-28	2	-5/+21
* \|	Improvements and bugfixes for generate blocks with local signals	Clifford Wolf	2013-03-26	1	-3/+1
* \|	Fixed handling of unconditional generate blocks	Clifford Wolf	2013-03-26	2	-1/+19
\|/
*	Added nosync attribute and some async reset related fixes	Clifford Wolf	2013-03-25	3	-34/+16
*	Added mem2reg option to verilog frontend	Clifford Wolf	2013-03-24	3	-10/+17
*	Another fix in mem2reg ast simplify logic	Clifford Wolf	2013-03-24	1	-1/+3
*	Improved mem2reg handling in ast simplifier	Clifford Wolf	2013-03-24	2	-5/+35
*	Tiny fixes to verilog parser	Clifford Wolf	2013-03-23	1	-0/+3
*	Moved stand-alone libs to libs/ directory and added libs/subcircuit	Clifford Wolf	2013-02-27	3	-3/+3
*	Added support for verilog genblock[index].member syntax	Clifford Wolf	2013-02-26	3	-1/+17
*	initial import	Clifford Wolf	2013-01-05	5	-0/+3227