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| author | Clifford Wolf <clifford@clifford.at> | 2013-07-09 23:53:55 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2013-07-09 23:53:55 +0200 |
| commit | ed62fcdbe224207434c5f643734f2627264826c5 (patch) | |
| tree | 818f91d9783e2772e5fda12c255cfd46b89f97ad /frontends/ast | |
| parent | 5dab327b30cb1d864297b22a15f0fce4b374a841 (diff) | |
| download | yosys-ed62fcdbe224207434c5f643734f2627264826c5.tar.gz yosys-ed62fcdbe224207434c5f643734f2627264826c5.tar.bz2 yosys-ed62fcdbe224207434c5f643734f2627264826c5.zip | |
Fixed sign propagation in bit-wise operators
Diffstat (limited to 'frontends/ast')
| -rw-r--r-- | frontends/ast/genrtlil.cc | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/frontends/ast/genrtlil.cc b/frontends/ast/genrtlil.cc index 830778227..7a9c8ba64 100644 --- a/frontends/ast/genrtlil.cc +++ b/frontends/ast/genrtlil.cc @@ -896,6 +896,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint) int width = std::max(left.width, right.width); if (width_hint > 0) width = width_hint; + is_signed = children[0]->is_signed && children[1]->is_signed; return binop2rtlil(this, type_name, width, left, right); } |