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| author | Clifford Wolf <clifford@clifford.at> | 2013-07-07 15:40:26 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2013-07-07 15:40:26 +0200 |
| commit | eff68560a2914791c8d0377edb5922fd5077f4f3 (patch) | |
| tree | 2a8a1727ee54076be19d805e7d845e7741efbe83 /frontends/ast | |
| parent | 52d21a63ca7eaf153ed0ee24e3aa355e8deb48cc (diff) | |
| download | yosys-eff68560a2914791c8d0377edb5922fd5077f4f3.tar.gz yosys-eff68560a2914791c8d0377edb5922fd5077f4f3.tar.bz2 yosys-eff68560a2914791c8d0377edb5922fd5077f4f3.zip | |
Fixed AST_CONSTANT node generation
Diffstat (limited to 'frontends/ast')
| -rw-r--r-- | frontends/ast/ast.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/frontends/ast/ast.cc b/frontends/ast/ast.cc index f7a39cf19..3e9ea50ac 100644 --- a/frontends/ast/ast.cc +++ b/frontends/ast/ast.cc @@ -661,7 +661,7 @@ AstNode *AstNode::mkconst_bits(const std::vector<RTLIL::State> &v, bool is_signe node->integer |= (node->bits.back() == RTLIL::S1) << i; } node->range_valid = true; - node->range_left = node->bits.size(); + node->range_left = node->bits.size()-1; node->range_right = 0; return node; } |