iCE40/yosys - [no description]

	Commit message (Expand)	Author	Age	Files	Lines
*	Implemented dynamic bit-/part-select for memory writes	Clifford Wolf	2014-07-17	1	-2/+26
*	Added support for bit/part select to mem2reg rewriter	Clifford Wolf	2014-07-17	1	-0/+9
*	Added support for constant bit- or part-select for memory writes	Clifford Wolf	2014-07-17	1	-9/+36
*	changes in verilog frontend for new $mem/$memwr WR_EN interface	Clifford Wolf	2014-07-16	2	-7/+6
*	Fixed processing of initial values for block-local variables	Clifford Wolf	2014-07-11	1	-0/+5
*	Fixed handling of mixed real/int ternary expressions	Clifford Wolf	2014-06-25	1	-0/+16
*	More found_real-related fixes to AstNode::detectSignWidthWorker	Clifford Wolf	2014-06-24	1	-6/+6
*	fixed signdness detection for expressions with reals	Clifford Wolf	2014-06-21	1	-2/+8
*	Added AstNode::MEM2REG_FL_CMPLX_LHS	Clifford Wolf	2014-06-17	2	-0/+23
*	Improved handling of relational op of real values	Clifford Wolf	2014-06-17	1	-8/+9
*	Improved ternary support for real values	Clifford Wolf	2014-06-16	1	-13/+24
*	Use undef (x/z vs. NaN) rules for real values from IEEE Std 1800-2012	Clifford Wolf	2014-06-16	2	-0/+11
*	Added found_real feature to AstNode::detectSignWidth	Clifford Wolf	2014-06-16	2	-6/+11
*	Improved AstNode::realAsConst for large numbers	Clifford Wolf	2014-06-15	1	-1/+1
*	Improved AstNode::asReal for large integers	Clifford Wolf	2014-06-15	2	-10/+13
*	improved (fixed) conversion of real values to bit vectors	Clifford Wolf	2014-06-14	4	-11/+30
*	Fixed relational operators for const real expressions	Clifford Wolf	2014-06-14	1	-8/+8
*	Added support for math functions	Clifford Wolf	2014-06-14	1	-0/+70
*	Added handling of real-valued parameters/localparams	Clifford Wolf	2014-06-14	2	-17/+47
*	Implemented more real arithmetic	Clifford Wolf	2014-06-14	1	-27/+70
*	Implemented basic real arithmetic	Clifford Wolf	2014-06-14	3	-6/+51
*	Added real->int convertion in ast genrtlil	Clifford Wolf	2014-06-14	1	-0/+12
*	Added Verilog lexer and parser support for real values	Clifford Wolf	2014-06-13	2	-0/+7
*	Add support for cell arrays	Clifford Wolf	2014-06-07	3	-0/+27
*	Added support for repeat stmt in const functions	Clifford Wolf	2014-06-07	1	-0/+19
*	further improved const function support	Clifford Wolf	2014-06-07	3	-17/+22
*	improved const function support	Clifford Wolf	2014-06-06	3	-5/+41
*	fix functions with no block (but single statement, loop, etc.)	Clifford Wolf	2014-06-06	1	-11/+4
*	improved ast simplify of const functions	Clifford Wolf	2014-06-06	1	-7/+28
*	added while and repeat support to verilog parser	Clifford Wolf	2014-06-06	2	-0/+2
*	Include id2ast pointers when dumping AST	Clifford Wolf	2014-03-05	1	-0/+6
*	Fixed merging of compatible wire decls in AST frontend	Clifford Wolf	2014-03-05	1	-1/+4
*	Bugfix in recursive AST simplification	Clifford Wolf	2014-03-05	1	-10/+22
*	Fixed bit-extending in $mux argument (use $bu0 instead of $pos)	Clifford Wolf	2014-02-26	1	-5/+5
*	Don't blow up constants unneccessarily in Verilog frontend	Clifford Wolf	2014-02-24	1	-1/+1
*	Fixed bug in generation of undefs for $memwr MUXes	Clifford Wolf	2014-02-22	1	-4/+6
*	Cleanups in handling of read_verilog -defer and -icells	Clifford Wolf	2014-02-20	1	-6/+7
*	Added Verilog support for "`default_nettype none"	Clifford Wolf	2014-02-17	3	-6/+13
*	Improved support for constant functions	Clifford Wolf	2014-02-16	1	-1/+50
*	Correctly convert constants to RTLIL (fixed undef handling)	Clifford Wolf	2014-02-15	1	-11/+1
*	Be more conservative with new const-function code	Clifford Wolf	2014-02-14	1	-1/+5
*	Added support for FOR loops in function calls in parameters	Clifford Wolf	2014-02-14	3	-0/+43
*	Created basic support for function calls in parameter values	Clifford Wolf	2014-02-14	4	-49/+184
*	Implemented read_verilog -defer	Clifford Wolf	2014-02-13	2	-58/+79
*	Fixed gcc compiler warnings with release build	Clifford Wolf	2014-02-06	1	-1/+1
*	Fixed bug in sequential sat proofs and improved handling of asserts	Clifford Wolf	2014-02-04	1	-0/+2
*	Added TRANSPARENT parameter to $memrd (and RD_TRANSPARENT to $mem)	Clifford Wolf	2014-02-03	1	-0/+1
*	Added constant size expression support of sized constants	Clifford Wolf	2014-02-01	4	-0/+22
*	Bugfix in name resolution with generate blocks	Clifford Wolf	2014-01-30	1	-1/+1
*	Added read_verilog -icells option	Clifford Wolf	2014-01-29	3	-5/+11