iCE40/yosys - [no description]

	Commit message (Expand)	Author	Age	Files	Lines
*	Do not the 'z' modifier in format string (another win32 fix)	Clifford Wolf	2014-10-11	1	-2/+2
*	Renamed SIZE() to GetSize() because of name collision on Win32	Clifford Wolf	2014-10-10	3	-20/+20
*	namespace Yosys	Clifford Wolf	2014-09-27	1	-0/+8
*	Another $clog2 bugfix	Clifford Wolf	2014-09-08	1	-0/+2
*	Fixed $clog2 (off by one error)	Clifford Wolf	2014-09-06	1	-2/+2
*	Fixed assignment of out-of bounds array element	Clifford Wolf	2014-09-06	1	-2/+26
*	Corrected spelling mistakes found by lintian	Ruben Undheim	2014-09-06	1	-1/+1
*	Removed $bu0 cell type	Clifford Wolf	2014-09-04	1	-5/+5
*	Added emscripten (emcc) support to build system and some build fixes	Clifford Wolf	2014-08-22	2	-1/+17
*	Archibald Rust and Clifford Wolf: ffi-based dpi_call()	Clifford Wolf	2014-08-22	1	-6/+90
*	Fixed small memory leak in ast simplify	Clifford Wolf	2014-08-21	1	-3/+3
*	Added support for DPI function with different names in C and Verilog	Clifford Wolf	2014-08-21	1	-4/+4
*	Added AstNode::asInt()	Clifford Wolf	2014-08-21	3	-2/+24
*	Fixed memory leak in DPI function calls	Clifford Wolf	2014-08-21	1	-0/+4
*	Added Verilog/AST support for DPI functions (dpi_call() still unimplemented)	Clifford Wolf	2014-08-21	6	-2/+81
*	Added support for global tasks and functions	Clifford Wolf	2014-08-21	1	-12/+26
*	Added "via_celltype" attribute on task/func	Clifford Wolf	2014-08-18	1	-6/+69
*	Added const folding of AST_CASE to AST simplifier	Clifford Wolf	2014-08-18	3	-1/+41
*	Improved AST ProcessGenerator performance	Clifford Wolf	2014-08-17	1	-3/+3
*	Use stackmap<> in AST ProcessGenerator	Clifford Wolf	2014-08-17	3	-24/+22
*	AST ProcessGenerator: replaced subst__{from,to} with subst__map	Clifford Wolf	2014-08-16	1	-41/+26
*	Fixed bug in "read_verilog -ignore_redef"	Clifford Wolf	2014-08-15	1	-1/+1
*	Added RTLIL::SigSpec::to_sigbit_map()	Clifford Wolf	2014-08-14	1	-11/+3
*	Changed the AST genWidthRTLIL subst interface to use a std::map	Clifford Wolf	2014-08-14	3	-21/+31
*	Fixed handling of task outputs	Clifford Wolf	2014-08-14	1	-2/+4
*	Added module->ports	Clifford Wolf	2014-08-14	1	-0/+1
*	Added AST_MULTIRANGE (arrays with more than 1 dimension)	Clifford Wolf	2014-08-06	3	-1/+62
*	Improved scope resolution of local regs in Verilog+AST frontend	Clifford Wolf	2014-08-05	2	-7/+26
*	Fixed AST handling of variables declared inside a functions main block	Clifford Wolf	2014-08-05	1	-3/+3
*	More bugfixes related to new RTLIL::IdString	Clifford Wolf	2014-08-02	1	-7/+7
*	More cleanups related to RTLIL::IdString usage	Clifford Wolf	2014-08-02	1	-6/+6
*	Preparations for RTLIL::IdString redesign: cleanup of existing code	Clifford Wolf	2014-08-02	2	-3/+3
*	Replaced sha1 implementation	Clifford Wolf	2014-08-01	1	-27/+2
*	Renamed port access function on RTLIL::Cell, added param access functions	Clifford Wolf	2014-07-31	1	-22/+22
*	Added module->design and cell->module, wire->module pointers	Clifford Wolf	2014-07-31	1	-5/+5
*	Moved some stuff to kernel/yosys.{h,cc}, using Yosys:: namespace	Clifford Wolf	2014-07-31	4	-39/+55
*	Added $shift and $shiftx cell types (needed for correct part select behavior)	Clifford Wolf	2014-07-29	1	-5/+11
*	Removed left over debug code	Clifford Wolf	2014-07-28	2	-2/+0
*	Fixed part selects of parameters	Clifford Wolf	2014-07-28	2	-7/+31
*	Set results of out-of-bounds static bit/part select to undef	Clifford Wolf	2014-07-28	1	-5/+31
*	Fixed RTLIL code generator for part select of parameter	Clifford Wolf	2014-07-28	1	-2/+2
*	Fixed width detection for part selects	Clifford Wolf	2014-07-28	1	-2/+2
*	Added support for "upto" wires to Verilog front- and back-end	Clifford Wolf	2014-07-28	4	-13/+17
*	Added wire->upto flag for signals such as "wire [0:7] x;"	Clifford Wolf	2014-07-28	1	-0/+3
*	Using log_assert() instead of assert()	Clifford Wolf	2014-07-28	3	-31/+30
*	Fixed signdness detection of expressions with bit- and part-selects	Clifford Wolf	2014-07-28	1	-0/+1
*	Added proper Design->addModule interface	Clifford Wolf	2014-07-27	1	-0/+1
*	Refactoring: Renamed RTLIL::Design::modules to modules_	Clifford Wolf	2014-07-27	1	-5/+5
*	Refactoring: Renamed RTLIL::Module::wires to wires_	Clifford Wolf	2014-07-27	1	-5/+5
*	Changed a lot of code to the new RTLIL::Wire constructors	Clifford Wolf	2014-07-26	1	-13/+9