| Commit message (Expand) | Author | Age | Files | Lines |
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| | * | | ast: simplify to fully populate dynamic slicing case transformation | Eddie Hung | 2020-03-31 | 1 | -1/+1 |
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| * | | Merge pull request #1783 from boqwxp/astcc_cleanup | Eddie Hung | 2020-03-30 | 1 | -13/+20 |
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| | * | | Add explanatory comment about inefficient wire removal and remove superfluous... | Alberto Gonzalez | 2020-03-30 | 1 | -4/+8 |
| | * | | Revert over-aggressive change to a more modest cleanup. | Alberto Gonzalez | 2020-03-27 | 1 | -2/+3 |
| | * | | Clean up pseudo-private member usage in `frontends/ast/ast.cc`. | Alberto Gonzalez | 2020-03-19 | 1 | -11/+13 |
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| * | | Merge pull request #1607 from whitequark/simplify-simplify-meminit | Claire Wolf | 2020-03-27 | 1 | -63/+82 |
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| | * | | ast: avoid intermediate wires/assigns when lowering to AST_MEMINIT. | whitequark | 2020-02-07 | 1 | -65/+84 |
| * | | | Simplify was not being called for packages. Broke typedef enums. | Peter Crozier | 2020-03-22 | 1 | -5/+8 |
| * | | | Fix NDEBUG warnings | Eddie Hung | 2020-03-19 | 1 | -1/+1 |
| * | | | Add precise locations for asserts | huaixv | 2020-03-19 | 1 | -0/+1 |
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| * | | Merge pull request #1718 from boqwxp/precise_locations | Claire Wolf | 2020-03-03 | 4 | -267/+253 |
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| | * | | Closes #1717. Add more precise Verilog source location information to AST and... | Alberto Gonzalez | 2020-02-23 | 4 | -267/+253 |
| * | | | Merge pull request #1681 from YosysHQ/eddie/fix1663 | Claire Wolf | 2020-03-03 | 1 | -15/+13 |
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| | * | | | verilog: instead of modifying localparam size, extend init constant expr | Eddie Hung | 2020-02-05 | 1 | -15/+13 |
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| * | | | Merge pull request #1724 from YosysHQ/eddie/abc9_specify | Eddie Hung | 2020-03-02 | 2 | -12/+20 |
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| | * | | | ast: quiet down when deriving blackbox modules | Eddie Hung | 2020-02-27 | 2 | -12/+20 |
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| * | | | ast: fixes #1710; do not generate RTLIL for unreachable ternary | Eddie Hung | 2020-02-27 | 1 | -9/+22 |
| * | | | Comment out log() | Eddie Hung | 2020-02-27 | 1 | -1/+1 |
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| * | | Merge pull request #1703 from YosysHQ/eddie/specify_improve | Eddie Hung | 2020-02-21 | 1 | -7/+11 |
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| | * | | verilog: fix $specify3 check | Eddie Hung | 2020-02-13 | 1 | -7/+11 |
| * | | | Merge pull request #1642 from jjj11x/jjj11x/sv-enum | Claire Wolf | 2020-02-20 | 4 | -16/+221 |
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| | * | | remove unnecessary blank line | Jeff Wang | 2020-02-17 | 1 | -2/+1 |
| | * | | add attributes for enumerated values in ilang | Jeff Wang | 2020-02-17 | 2 | -1/+68 |
| | * | | separate out enum_item/param implementation when they should be different | Jeff Wang | 2020-02-17 | 1 | -7/+16 |
| | * | | fix bug introduced by not taking all of PeterCrozier's changes in 16ea4ea6 | Jeff Wang | 2020-01-17 | 1 | -4/+6 |
| | * | | fix enum in generate blocks | Jeff Wang | 2020-01-16 | 1 | -0/+20 |
| | * | | allow enums to be declared at toplevel scope | Jeff Wang | 2020-01-16 | 1 | -0/+7 |
| | * | | partial rebase of PeterCrozier's enum work onto current master | Jeff Wang | 2020-01-16 | 4 | -16/+117 |
| * | | | Modified $readmem[hb] to use '\' or '/' according the OS | Rodrigo Alejandro Melo | 2020-02-06 | 1 | -1/+6 |
| * | | | Merge branch 'master' of https://github.com/YosysHQ/yosys | Rodrigo Alejandro Melo | 2020-02-03 | 2 | -93/+110 |
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| | * | | ast: Add support for $sformatf system function | David Shah | 2020-01-19 | 2 | -93/+110 |
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| * | | Replaced strlen by GetSize into simplify.cc | Rodrigo Alejandro Melo | 2020-02-03 | 1 | -2/+2 |
| * | | Fixed a bug in the new feature of $readmem[hb] when an empty string is provided | Rodrigo Alejandro Melo | 2020-02-01 | 1 | -1/+1 |
| * | | Modified the new search for files of $readmem[hb] to be backward compatible | Rodrigo Alejandro Melo | 2020-01-31 | 1 | -3/+7 |
| * | | $readmem[hb] file inclusion is now relative to the Verilog file | Rodrigo Alejandro Melo | 2020-01-31 | 1 | -1/+2 |
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| * | Stray log_dump | Eddie Hung | 2019-12-11 | 1 | -1/+0 |
| * | Preserve size of $genval$-s in for loops | Eddie Hung | 2019-12-11 | 1 | -0/+17 |
| * | Use "(id)" instead of "id" for types as temporary hack | Clifford Wolf | 2019-10-14 | 4 | -9/+118 |
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| | * | frontends/ast: code style | David Shah | 2019-10-03 | 1 | -2/+1 |
| | * | sv: Fix typedefs in blocks | David Shah | 2019-10-03 | 1 | -2/+2 |
| | * | sv: Add support for memories of a typedef | David Shah | 2019-10-03 | 1 | -6/+20 |
| | * | sv: Add support for memory typedefs | David Shah | 2019-10-03 | 1 | -2/+15 |
| | * | sv: Fix typedefs in packages | David Shah | 2019-10-03 | 1 | -4/+10 |
| | * | sv: Fix typedef parameters | David Shah | 2019-10-03 | 1 | -2/+31 |
| | * | sv: Switch parser to glr, prep for typedef | David Shah | 2019-10-03 | 4 | -7/+55 |
| * | | Fix for svinterfaces | Eddie Hung | 2019-09-30 | 1 | -2/+8 |
| * | | module->derive() to be lazy and not touch ast if already derived | Eddie Hung | 2019-09-30 | 2 | -33/+51 |
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| * | Fix handling of read_verilog config in AstModule::reprocess_module(), fixes #... | Clifford Wolf | 2019-09-20 | 2 | -18/+30 |
| * | Fix handling of range selects on loop variables, fixes #1372 | Clifford Wolf | 2019-09-16 | 1 | -2/+9 |
| * | Merge pull request #1350 from YosysHQ/clifford/fixsby59 | Clifford Wolf | 2019-09-05 | 1 | -7/+18 |
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