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* Added deep recursion warning to AST simplifyClifford Wolf2015-02-201-1/+7
* Parser support for complex delay expressionsClifford Wolf2015-02-201-1/+1
* Various fixes for memories with offsetsClifford Wolf2015-02-141-0/+1
* Added "read_verilog -nomeminit" and "nomeminit" attributeClifford Wolf2015-02-141-1/+5
* Creating $meminit cells in verilog front-endClifford Wolf2015-02-141-25/+44
* Added AstNode::simplify() recursion counterClifford Wolf2015-02-131-2/+10
* Added ENABLE_NDEBUG makefile optionsClifford Wolf2015-01-241-0/+2
* Ignoring more system task and functionsClifford Wolf2015-01-151-1/+3
* Fixed handling of "input foo; reg [0:0] foo;"Clifford Wolf2015-01-151-0/+7
* Consolidate "Blocking assignment to memory.." msgs for the same lineClifford Wolf2015-01-151-3/+9
* dict/pool changes in astClifford Wolf2014-12-291-12/+12
* Fixed mem2reg warning messageClifford Wolf2014-12-271-3/+3
* Added log_warning() APIClifford Wolf2014-11-091-4/+4
* AST simplifier: optimize constant AST_CASE nodes before recursively descendingClifford Wolf2014-10-291-31/+35
* Improvements in $readmem[bh] implementationClifford Wolf2014-10-261-8/+13
* Added support for $readmemh/$readmembClifford Wolf2014-10-261-0/+112
* Fixed various VS warningsClifford Wolf2014-10-181-1/+1
* Wrapped math in int constructorWilliam Speirs2014-10-171-1/+1
* Fixed handling of invalid array access in mem2reg codeClifford Wolf2014-10-161-3/+14
* Renamed SIZE() to GetSize() because of name collision on Win32Clifford Wolf2014-10-101-10/+10
* Another $clog2 bugfixClifford Wolf2014-09-081-0/+2
* Fixed $clog2 (off by one error)Clifford Wolf2014-09-061-2/+2
* Corrected spelling mistakes found by lintianRuben Undheim2014-09-061-1/+1
* Fixed small memory leak in ast simplifyClifford Wolf2014-08-211-3/+3
* Added support for DPI function with different names in C and VerilogClifford Wolf2014-08-211-4/+4
* Fixed memory leak in DPI function callsClifford Wolf2014-08-211-0/+4
* Added Verilog/AST support for DPI functions (dpi_call() still unimplemented)Clifford Wolf2014-08-211-2/+30
* Added "via_celltype" attribute on task/funcClifford Wolf2014-08-181-6/+69
* Added const folding of AST_CASE to AST simplifierClifford Wolf2014-08-181-1/+32
* Fixed handling of task outputsClifford Wolf2014-08-141-2/+4
* Added AST_MULTIRANGE (arrays with more than 1 dimension)Clifford Wolf2014-08-061-1/+51
* Improved scope resolution of local regs in Verilog+AST frontendClifford Wolf2014-08-051-6/+25
* Fixed AST handling of variables declared inside a functions main blockClifford Wolf2014-08-051-3/+3
* More bugfixes related to new RTLIL::IdStringClifford Wolf2014-08-021-7/+7
* Preparations for RTLIL::IdString redesign: cleanup of existing codeClifford Wolf2014-08-021-1/+1
* Moved some stuff to kernel/yosys.{h,cc}, using Yosys:: namespaceClifford Wolf2014-07-311-28/+32
* Removed left over debug codeClifford Wolf2014-07-281-1/+0
* Fixed part selects of parametersClifford Wolf2014-07-281-2/+21
* Added support for "upto" wires to Verilog front- and back-endClifford Wolf2014-07-281-0/+4
* Using log_assert() instead of assert()Clifford Wolf2014-07-281-17/+17
* Fixed two memory leaks in ast simplifyClifford Wolf2014-07-251-1/+6
* Various small fixes (from gcc compiler warnings)Clifford Wolf2014-07-231-1/+1
* Implemented dynamic bit-/part-select for memory writesClifford Wolf2014-07-171-2/+26
* Added support for bit/part select to mem2reg rewriterClifford Wolf2014-07-171-0/+9
* Added support for constant bit- or part-select for memory writesClifford Wolf2014-07-171-9/+36
* changes in verilog frontend for new $mem/$memwr WR_EN interfaceClifford Wolf2014-07-161-4/+6
* Fixed processing of initial values for block-local variablesClifford Wolf2014-07-111-0/+5
* Fixed handling of mixed real/int ternary expressionsClifford Wolf2014-06-251-0/+16
* Added AstNode::MEM2REG_FL_CMPLX_LHSClifford Wolf2014-06-171-0/+22
* Improved handling of relational op of real valuesClifford Wolf2014-06-171-8/+9