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| author | Clifford Wolf <clifford@clifford.at> | 2014-07-28 14:25:03 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2014-07-28 14:25:03 +0200 |
| commit | 27a872d1e7041be4894bc643a420587ff5894125 (patch) | |
| tree | 430d0411eaa4c4f6893576e2179d2eee93726def /frontends/ast/simplify.cc | |
| parent | 3c45277ee0f5822181c6058f679de632f834e7d2 (diff) | |
| download | yosys-27a872d1e7041be4894bc643a420587ff5894125.tar.gz yosys-27a872d1e7041be4894bc643a420587ff5894125.tar.bz2 yosys-27a872d1e7041be4894bc643a420587ff5894125.zip | |
Added support for "upto" wires to Verilog front- and back-end
Diffstat (limited to 'frontends/ast/simplify.cc')
| -rw-r--r-- | frontends/ast/simplify.cc | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/frontends/ast/simplify.cc b/frontends/ast/simplify.cc index 2a55adeff..7aa6d24c3 100644 --- a/frontends/ast/simplify.cc +++ b/frontends/ast/simplify.cc @@ -504,6 +504,7 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage, if (type == AST_RANGE) { bool old_range_valid = range_valid; range_valid = false; + range_swapped = false; range_left = -1; range_right = 0; log_assert(children.size() >= 1); @@ -525,6 +526,7 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage, int tmp = range_right; range_right = range_left; range_left = tmp; + range_swapped = true; } } @@ -535,6 +537,7 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage, if (!range_valid) did_something = true; range_valid = true; + range_swapped = children[0]->range_swapped; range_left = children[0]->range_left; range_right = children[0]->range_right; } @@ -542,6 +545,7 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage, if (!range_valid) did_something = true; range_valid = true; + range_swapped = false; range_left = 0; range_right = 0; } |