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* Renamed SIZE() to GetSize() because of name collision on Win32Clifford Wolf2014-10-101-10/+10
* Another $clog2 bugfixClifford Wolf2014-09-081-0/+2
* Fixed $clog2 (off by one error)Clifford Wolf2014-09-061-2/+2
* Corrected spelling mistakes found by lintianRuben Undheim2014-09-061-1/+1
* Fixed small memory leak in ast simplifyClifford Wolf2014-08-211-3/+3
* Added support for DPI function with different names in C and VerilogClifford Wolf2014-08-211-4/+4
* Fixed memory leak in DPI function callsClifford Wolf2014-08-211-0/+4
* Added Verilog/AST support for DPI functions (dpi_call() still unimplemented)Clifford Wolf2014-08-211-2/+30
* Added "via_celltype" attribute on task/funcClifford Wolf2014-08-181-6/+69
* Added const folding of AST_CASE to AST simplifierClifford Wolf2014-08-181-1/+32
* Fixed handling of task outputsClifford Wolf2014-08-141-2/+4
* Added AST_MULTIRANGE (arrays with more than 1 dimension)Clifford Wolf2014-08-061-1/+51
* Improved scope resolution of local regs in Verilog+AST frontendClifford Wolf2014-08-051-6/+25
* Fixed AST handling of variables declared inside a functions main blockClifford Wolf2014-08-051-3/+3
* More bugfixes related to new RTLIL::IdStringClifford Wolf2014-08-021-7/+7
* Preparations for RTLIL::IdString redesign: cleanup of existing codeClifford Wolf2014-08-021-1/+1
* Moved some stuff to kernel/yosys.{h,cc}, using Yosys:: namespaceClifford Wolf2014-07-311-28/+32
* Removed left over debug codeClifford Wolf2014-07-281-1/+0
* Fixed part selects of parametersClifford Wolf2014-07-281-2/+21
* Added support for "upto" wires to Verilog front- and back-endClifford Wolf2014-07-281-0/+4
* Using log_assert() instead of assert()Clifford Wolf2014-07-281-17/+17
* Fixed two memory leaks in ast simplifyClifford Wolf2014-07-251-1/+6
* Various small fixes (from gcc compiler warnings)Clifford Wolf2014-07-231-1/+1
* Implemented dynamic bit-/part-select for memory writesClifford Wolf2014-07-171-2/+26
* Added support for bit/part select to mem2reg rewriterClifford Wolf2014-07-171-0/+9
* Added support for constant bit- or part-select for memory writesClifford Wolf2014-07-171-9/+36
* changes in verilog frontend for new $mem/$memwr WR_EN interfaceClifford Wolf2014-07-161-4/+6
* Fixed processing of initial values for block-local variablesClifford Wolf2014-07-111-0/+5
* Fixed handling of mixed real/int ternary expressionsClifford Wolf2014-06-251-0/+16
* Added AstNode::MEM2REG_FL_CMPLX_LHSClifford Wolf2014-06-171-0/+22
* Improved handling of relational op of real valuesClifford Wolf2014-06-171-8/+9
* Improved ternary support for real valuesClifford Wolf2014-06-161-13/+24
* Use undef (x/z vs. NaN) rules for real values from IEEE Std 1800-2012Clifford Wolf2014-06-161-0/+9
* Improved AstNode::asReal for large integersClifford Wolf2014-06-151-1/+1
* improved (fixed) conversion of real values to bit vectorsClifford Wolf2014-06-141-7/+7
* Fixed relational operators for const real expressionsClifford Wolf2014-06-141-8/+8
* Added support for math functionsClifford Wolf2014-06-141-0/+70
* Added handling of real-valued parameters/localparamsClifford Wolf2014-06-141-13/+38
* Implemented more real arithmeticClifford Wolf2014-06-141-27/+70
* Implemented basic real arithmeticClifford Wolf2014-06-141-5/+17
* Add support for cell arraysClifford Wolf2014-06-071-0/+25
* Added support for repeat stmt in const functionsClifford Wolf2014-06-071-0/+19
* further improved const function supportClifford Wolf2014-06-071-11/+16
* improved const function supportClifford Wolf2014-06-061-4/+39
* fix functions with no block (but single statement, loop, etc.)Clifford Wolf2014-06-061-11/+4
* improved ast simplify of const functionsClifford Wolf2014-06-061-7/+28
* Fixed merging of compatible wire decls in AST frontendClifford Wolf2014-03-051-1/+4
* Bugfix in recursive AST simplificationClifford Wolf2014-03-051-10/+22
* Fixed bug in generation of undefs for $memwr MUXesClifford Wolf2014-02-221-4/+6
* Improved support for constant functionsClifford Wolf2014-02-161-1/+50