| Commit message (Expand) | Author | Age | Files | Lines |
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| * | verilog: fix const func eval with upto variables | Zachary Snow | 2022-02-11 | 1 | -0/+1 |
| * | verilog: use derived module info to elaborate cell connections | Zachary Snow | 2021-10-25 | 1 | -2/+12 |
| * | Split out logic for reprocessing an AstModule | Rupert Swarbrick | 2021-10-25 | 1 | -1/+13 |
| * | Generate an RTLIL representation of bind constructs | Rupert Swarbrick | 2021-08-13 | 1 | -0/+3 |
| * | verilog: Emit $meminit_v2 cell. | Marcelina Kościelnicka | 2021-07-28 | 1 | -1/+1 |
| * | Add support for parsing the SystemVerilog 'bind' construct | Rupert Swarbrick | 2021-07-16 | 1 | -1/+2 |
| * | sv: fix two struct access bugs | Zachary Snow | 2021-07-15 | 1 | -0/+3 |
| * | Merge pull request #2817 from YosysHQ/claire/fixemails | Claire Xen | 2021-06-09 | 1 | -1/+1 |
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| | * | Fixing old e-mail addresses and deadnames | Claire Xenia Wolf | 2021-06-08 | 1 | -1/+1 |
| * | | verilog: check for module scope identifiers during width detection | Zachary Snow | 2021-06-08 | 1 | -0/+3 |
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| * | verilog: fix case expression sign and width handling | Zachary Snow | 2021-05-25 | 1 | -1/+1 |
| * | Change the type of current_module to Module | Rupert Swarbrick | 2021-05-13 | 1 | -1/+1 |
| * | verilog: Use proc memory writes in the frontend. | Marcelina Kościelnicka | 2021-03-08 | 1 | -0/+2 |
| * | frontend: Make helper functions for printing locations. | Marcelina Kościelnicka | 2021-02-23 | 1 | -0/+6 |
| * | Merge pull request #2594 from zachjs/func-arg-width | whitequark | 2021-02-23 | 1 | -1/+7 |
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| | * | verilog: fix sizing of constant args for tasks/functions | Zachary Snow | 2021-02-21 | 1 | -1/+7 |
| * | | verilog: support recursive functions using ternary expressions | Zachary Snow | 2021-02-12 | 1 | -0/+3 |
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| * | verilog: refactored constant function evaluation | Zachary Snow | 2021-02-04 | 1 | -4/+3 |
| * | verilog: significant block scoping improvements | Zachary Snow | 2021-01-31 | 1 | -2/+2 |
| * | verilog: improved support for recursive functions | Zachary Snow | 2020-12-31 | 1 | -0/+2 |
| * | Added $high(), $low(), $left(), $right() | Udi Finkelstein | 2020-09-15 | 1 | -0/+1 |
| * | Fix generate scoping issues | Zachary Snow | 2020-07-31 | 1 | -1/+1 |
| * | static cast: support changing size and signedness | Kazuki Sakamoto | 2020-06-19 | 1 | -0/+1 |
| * | Use C++11 final/override keywords. | whitequark | 2020-06-18 | 1 | -5/+5 |
| * | Add latch detection for use_case_method in part-select write, fixes #2040 | Claire Wolf | 2020-06-04 | 1 | -0/+1 |
| * | Generalise structs and add support for packed unions. | Peter Crozier | 2020-05-12 | 1 | -0/+1 |
| * | Implement SV structs. | Peter Crozier | 2020-05-08 | 1 | -2/+5 |
| * | Add AST_SELFSZ and improve handling of bit slices | Claire Wolf | 2020-05-02 | 1 | -0/+1 |
| * | Add "nowrshmsk" attribute, fix shift-and-mask bit slice write for signed offs... | Claire Wolf | 2020-05-02 | 1 | -0/+2 |
| * | Add LookaheadRewriter for proper bitselwrite support | Claire Wolf | 2020-04-16 | 1 | -0/+4 |
| * | kernel: more pass by const ref, more speedups | Eddie Hung | 2020-03-18 | 1 | -4/+4 |
| * | Merge pull request #1718 from boqwxp/precise_locations | Claire Wolf | 2020-03-03 | 1 | -1/+8 |
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| | * | Closes #1717. Add more precise Verilog source location information to AST and... | Alberto Gonzalez | 2020-02-23 | 1 | -1/+8 |
| * | | ast: quiet down when deriving blackbox modules | Eddie Hung | 2020-02-27 | 1 | -1/+1 |
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| * | Merge pull request #1642 from jjj11x/jjj11x/sv-enum | Claire Wolf | 2020-02-20 | 1 | -0/+7 |
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| | * | partial rebase of PeterCrozier's enum work onto current master | Jeff Wang | 2020-01-16 | 1 | -0/+7 |
| * | | ast: Add support for $sformatf system function | David Shah | 2020-01-19 | 1 | -0/+1 |
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| * | Use "(id)" instead of "id" for types as temporary hack | Clifford Wolf | 2019-10-14 | 1 | -2/+5 |
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| | * | sv: Switch parser to glr, prep for typedef | David Shah | 2019-10-03 | 1 | -2/+5 |
| * | | module->derive() to be lazy and not touch ast if already derived | Eddie Hung | 2019-09-30 | 1 | -1/+1 |
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| * | Fix handling of read_verilog config in AstModule::reprocess_module(), fixes #... | Clifford Wolf | 2019-09-20 | 1 | -0/+1 |
| * | Add "read_verilog -pwires" feature, closes #1106 | Clifford Wolf | 2019-06-19 | 1 | -3/+3 |
| * | Fixes and cleanups in AST_TECALL handling | Clifford Wolf | 2019-06-07 | 1 | -1/+0 |
| * | Merge branch 'pr_elab_sys_tasks' of https://github.com/udif/yosys into cliffo... | Clifford Wolf | 2019-06-07 | 1 | -1/+3 |
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| | * | Initial implementation of elaboration system tasks | Udi Finkelstein | 2019-05-03 | 1 | -1/+3 |
| * | | Merge branch 'master' into wandwor | Stefan Biereigel | 2019-05-27 | 1 | -1/+3 |
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| | * | | Added support for unsized constants, fixes #1022 | Miodrag Milanovic | 2019-05-27 | 1 | -1/+3 |
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| * | | remove leftovers from ast data structures | Stefan Biereigel | 2019-05-27 | 1 | -1/+0 |
| * | | fix indentation across files | Stefan Biereigel | 2019-05-23 | 1 | -1/+1 |
| * | | implementation for assignments working | Stefan Biereigel | 2019-05-23 | 1 | -0/+1 |
