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authorZachary Snow <zach@zachjs.com>2021-03-25 14:06:05 -0400
committerZachary Snow <zachary.j.snow@gmail.com>2021-05-25 16:16:46 -0400
commit0795b3ec076d8d2c0aa0d954b707271bd2f064bf (patch)
tree5b6c7eaef762a9dc76bb0507c76d0addcbdbb736 /frontends/ast/ast.h
parent15f35d6754af619accdf63030e0a5ad3085cec16 (diff)
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verilog: fix case expression sign and width handling
- The case expression and case item expressions are extended to the maximum width among them, and are only interpreted as signed if all of them are signed - Add overall width and sign detection for AST_CASE - Add sign argument to genWidthRTLIL helper - Coverage for both const and non-const case statements
Diffstat (limited to 'frontends/ast/ast.h')
-rw-r--r--frontends/ast/ast.h2
1 files changed, 1 insertions, 1 deletions
diff --git a/frontends/ast/ast.h b/frontends/ast/ast.h
index 069479353..9887d24ea 100644
--- a/frontends/ast/ast.h
+++ b/frontends/ast/ast.h
@@ -291,7 +291,7 @@ namespace AST
// for expressions the resulting signal vector is returned
// all generated cell instances, etc. are written to the RTLIL::Module pointed to by AST_INTERNAL::current_module
RTLIL::SigSpec genRTLIL(int width_hint = -1, bool sign_hint = false);
- RTLIL::SigSpec genWidthRTLIL(int width, const dict<RTLIL::SigBit, RTLIL::SigBit> *new_subst_ptr = NULL);
+ RTLIL::SigSpec genWidthRTLIL(int width, bool sgn, const dict<RTLIL::SigBit, RTLIL::SigBit> *new_subst_ptr = NULL);
// compare AST nodes
bool operator==(const AstNode &other) const;