| Commit message (Collapse) | Author | Age | Files | Lines | ||
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| * | | Merge pull request #513 from udif/pr_reg_wire_error | Clifford Wolf | 2018-08-15 | 1 | -1/+1 | |
| |\ \ | |/ |/| | Add error checking for reg/wire/logic misuse - PR now passes 'make test' (plus a new test) | |||||
| | * | Modified errors into warnings | Udi Finkelstein | 2018-06-05 | 1 | -1/+1 | |
| | | | | | | | | | No longer false warnings for memories and assertions | |||||
| | * | This PR should be the base for discussion, do not merge it yet! | Udi Finkelstein | 2018-03-11 | 1 | -1/+1 | |
| | | | | | | | | | | | | | | | | | | | | | | | | | It correctly detects reg/wire mix and incorrect use on blocking,nonblocking assignments within blocks and assign statements. What it DOES'T do: Detect registers connected to output ports of instances. Where it FAILS: memorty nonblocking assignments causes spurious (I assume??) errors on yosys-generated "_ADDR", "_DATA", "EN" signals. You can test it with tests/simple/reg_wire_error.v (look inside for the comments to enable/disable specific lines) | |||||
| * | | Replace -ignore_redef with -[no]overwrite | Clifford Wolf | 2018-05-03 | 1 | -1/+1 | |
| |/ | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| * | Bugfix in hierarchy handling of blackbox module ports | Clifford Wolf | 2018-01-05 | 1 | -1/+1 | |
| | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| * | Turned a few member functions into const, esp. dumpAst(), dumpVlog(). | Udi Finkelstein | 2017-09-30 | 1 | -7/+7 | |
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| * | Add $live and $fair cell types, add support for s_eventually keyword | Clifford Wolf | 2017-02-25 | 1 | -0/+2 | |
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| * | Add $cover cell type and SVA cover() support | Clifford Wolf | 2017-02-04 | 1 | -0/+1 | |
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| * | Avoid creation of bogus initial blocks for assert/assume in always @* | Clifford Wolf | 2016-09-06 | 1 | -0/+1 | |
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| * | Removed $predict again | Clifford Wolf | 2016-08-28 | 1 | -1/+0 | |
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| * | Another bugfix in mem2reg code | Clifford Wolf | 2016-08-21 | 1 | -1/+1 | |
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| * | Added "read_verilog -dump_rtlil" | Clifford Wolf | 2016-07-27 | 1 | -3/+5 | |
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| * | After reading the SV spec, using non-standard predict() instead of expect() | Clifford Wolf | 2016-07-21 | 1 | -1/+1 | |
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| * | Added basic support for $expect cells | Clifford Wolf | 2016-07-13 | 1 | -0/+1 | |
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| * | Added support for SystemVerilog packages with localparam definitions | Ruben Undheim | 2016-06-18 | 1 | -1/+3 | |
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| * | Fixed access-after-delete bug in mem2reg code | Clifford Wolf | 2016-05-27 | 1 | -0/+1 | |
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| * | Fixed handling of parameters and const functions in casex/casez pattern | Clifford Wolf | 2016-04-21 | 1 | -0/+2 | |
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| * | Spell check (by Larry Doolittle) | Clifford Wolf | 2015-08-14 | 1 | -1/+1 | |
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| * | Added WORDS parameter to $meminit | Clifford Wolf | 2015-07-31 | 1 | -1/+1 | |
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| * | Fixed nested mem2reg | Clifford Wolf | 2015-07-29 | 1 | -1/+1 | |
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| * | Fixed trailing whitespaces | Clifford Wolf | 2015-07-02 | 1 | -2/+2 | |
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| * | Added non-std verilog assume() statement | Clifford Wolf | 2015-02-26 | 1 | -0/+1 | |
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| * | Added "read_verilog -nomeminit" and "nomeminit" attribute | Clifford Wolf | 2015-02-14 | 1 | -3/+3 | |
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| * | Creating $meminit cells in verilog front-end | Clifford Wolf | 2015-02-14 | 1 | -1/+2 | |
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| * | dict/pool changes in ast | Clifford Wolf | 2014-12-29 | 1 | -4/+8 | |
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| * | Changed more code to dict<> and pool<> | Clifford Wolf | 2014-12-28 | 1 | -2/+2 | |
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| * | Added Yosys::{dict,nodict,vector} container types | Clifford Wolf | 2014-12-26 | 1 | -1/+1 | |
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| * | Added support for $readmemh/$readmemb | Clifford Wolf | 2014-10-26 | 1 | -0/+1 | |
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| * | Fixed handling of invalid array access in mem2reg code | Clifford Wolf | 2014-10-16 | 1 | -0/+1 | |
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| * | Added AstNode::asInt() | Clifford Wolf | 2014-08-21 | 1 | -0/+1 | |
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| * | Added Verilog/AST support for DPI functions (dpi_call() still unimplemented) | Clifford Wolf | 2014-08-21 | 1 | -0/+4 | |
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| * | Added const folding of AST_CASE to AST simplifier | Clifford Wolf | 2014-08-18 | 1 | -0/+1 | |
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| * | Use stackmap<> in AST ProcessGenerator | Clifford Wolf | 2014-08-17 | 1 | -2/+2 | |
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| * | Changed the AST genWidthRTLIL subst interface to use a std::map | Clifford Wolf | 2014-08-14 | 1 | -2/+3 | |
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| * | Added AST_MULTIRANGE (arrays with more than 1 dimension) | Clifford Wolf | 2014-08-06 | 1 | -0/+4 | |
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| * | Improved scope resolution of local regs in Verilog+AST frontend | Clifford Wolf | 2014-08-05 | 1 | -1/+1 | |
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| * | Moved some stuff to kernel/yosys.{h,cc}, using Yosys:: namespace | Clifford Wolf | 2014-07-31 | 1 | -0/+4 | |
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| * | Added support for "upto" wires to Verilog front- and back-end | Clifford Wolf | 2014-07-28 | 1 | -1/+1 | |
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| * | Added AstNode::MEM2REG_FL_CMPLX_LHS | Clifford Wolf | 2014-06-17 | 1 | -0/+1 | |
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| * | Added found_real feature to AstNode::detectSignWidth | Clifford Wolf | 2014-06-16 | 1 | -2/+2 | |
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| * | improved (fixed) conversion of real values to bit vectors | Clifford Wolf | 2014-06-14 | 1 | -0/+1 | |
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| * | Implemented basic real arithmetic | Clifford Wolf | 2014-06-14 | 1 | -0/+4 | |
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| * | Added Verilog lexer and parser support for real values | Clifford Wolf | 2014-06-13 | 1 | -0/+2 | |
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| * | Add support for cell arrays | Clifford Wolf | 2014-06-07 | 1 | -0/+1 | |
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| * | further improved const function support | Clifford Wolf | 2014-06-07 | 1 | -1/+1 | |
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| * | improved const function support | Clifford Wolf | 2014-06-06 | 1 | -0/+1 | |
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| * | added while and repeat support to verilog parser | Clifford Wolf | 2014-06-06 | 1 | -0/+1 | |
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| * | Added Verilog support for "`default_nettype none" | Clifford Wolf | 2014-02-17 | 1 | -3/+3 | |
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| * | Added support for FOR loops in function calls in parameters | Clifford Wolf | 2014-02-14 | 1 | -0/+1 | |
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| * | Created basic support for function calls in parameter values | Clifford Wolf | 2014-02-14 | 1 | -1/+6 | |
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index : iCE40/yosys | |
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