aboutsummaryrefslogtreecommitdiffstats
path: root/frontends/ast/ast.cc
Commit message (Expand)AuthorAgeFilesLines
...
* Support for 'modports' for System Verilog interfacesRuben Undheim2018-10-121-4/+36
* Synthesis support for SystemVerilog interfacesRuben Undheim2018-10-121-11/+122
* Added -no_dump_ptr flag for AST dump options in 'read_verilog'Udi Finkelstein2018-08-231-6/+9
* Merge pull request #513 from udif/pr_reg_wire_errorClifford Wolf2018-08-151-1/+7
|\
| * Modified errors into warningsUdi Finkelstein2018-06-051-0/+1
| * This PR should be the base for discussion, do not merge it yet!Udi Finkelstein2018-03-111-1/+6
* | Convert more log_error() to log_file_error() where possible.Henner Zeller2018-07-201-7/+6
* | Replace -ignore_redef with -[no]overwriteClifford Wolf2018-05-031-5/+13
|/
* Bugfix in hierarchy handling of blackbox module portsClifford Wolf2018-01-051-1/+1
* Turned a few member functions into const, esp. dumpAst(), dumpVlog().Udi Finkelstein2017-09-301-7/+7
* Add $live and $fair cell types, add support for s_eventually keywordClifford Wolf2017-02-251-0/+2
* Preserve string parametersClifford Wolf2017-02-231-2/+8
* Add $cover cell type and SVA cover() supportClifford Wolf2017-02-041-0/+1
* Added support for hierarchical defparamsClifford Wolf2016-11-151-2/+7
* Remember global declarations and defines accross read_verilog callsClifford Wolf2016-11-151-4/+2
* Added avail params to ilang format, check module params in 'hierarchy -check'Clifford Wolf2016-10-221-2/+7
* Avoid creation of bogus initial blocks for assert/assume in always @*Clifford Wolf2016-09-061-0/+1
* Removed $predict againClifford Wolf2016-08-281-1/+0
* Minor improvements to AstNode::dumpAst() and AstNode::dumpVlog()Clifford Wolf2016-08-211-4/+15
* Added "read_verilog -dump_rtlil"Clifford Wolf2016-07-271-5/+16
* After reading the SV spec, using non-standard predict() instead of expect()Clifford Wolf2016-07-211-1/+1
* Added basic support for $expect cellsClifford Wolf2016-07-131-0/+1
* A few modifications after pull request commentsRuben Undheim2016-06-181-2/+2
* Added support for SystemVerilog packages with localparam definitionsRuben Undheim2016-06-181-0/+12
* Include <cmath> in yosys.hClifford Wolf2016-05-081-9/+0
* Added "yosys -D" featureClifford Wolf2016-04-211-1/+1
* Fixed handling of parameters and const functions in casex/casez patternClifford Wolf2016-04-211-1/+10
* Fixed some visual studio warningsClifford Wolf2016-02-131-1/+1
* Fixed segfault in AstNode::asRealClifford Wolf2015-09-251-1/+1
* Fixed AstNode::mkconst_bits() segfault on zero-sized constantClifford Wolf2015-09-241-1/+1
* Another block of spelling fixesLarry Doolittle2015-08-141-4/+4
* Fixed trailing whitespacesClifford Wolf2015-07-021-3/+3
* Added non-std verilog assume() statementClifford Wolf2015-02-261-0/+1
* Added "read_verilog -nomeminit" and "nomeminit" attributeClifford Wolf2015-02-141-2/+6
* Creating $meminit cells in verilog front-endClifford Wolf2015-02-141-1/+2
* Added global yosys_celltypesClifford Wolf2014-12-291-1/+1
* dict/pool changes in astClifford Wolf2014-12-291-0/+4
* Changed more code to dict<> and pool<>Clifford Wolf2014-12-281-1/+1
* Added Yosys::{dict,nodict,vector} container typesClifford Wolf2014-12-261-1/+1
* Fixed constant "cond ? string1 : string2" with strings of different sizeClifford Wolf2014-10-251-0/+2
* minor indenting correctionsClifford Wolf2014-10-191-2/+2
* Builds on Mac 10.9.2 with LLVM 3.5.Parviz Palangpour2014-10-191-0/+5
* Do not the 'z' modifier in format string (another win32 fix)Clifford Wolf2014-10-111-2/+2
* Added emscripten (emcc) support to build system and some build fixesClifford Wolf2014-08-221-0/+4
* Added AstNode::asInt()Clifford Wolf2014-08-211-1/+22
* Added Verilog/AST support for DPI functions (dpi_call() still unimplemented)Clifford Wolf2014-08-211-0/+1
* Added support for global tasks and functionsClifford Wolf2014-08-211-12/+26
* Added const folding of AST_CASE to AST simplifierClifford Wolf2014-08-181-0/+8
* Use stackmap<> in AST ProcessGeneratorClifford Wolf2014-08-171-1/+1
* Fixed bug in "read_verilog -ignore_redef"Clifford Wolf2014-08-151-1/+1
generated by cgit v1.2.3 (git 2.25.1) at 2024-08-01 23:19:19 +0000