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* Merge pull request #800 from whitequark/write_verilog_tribufClifford Wolf2019-01-271-0/+12
|\ | | | | write_verilog: write $tribuf cell as ternary
| * write_verilog: write $tribuf cell as ternary.whitequark2019-01-271-0/+12
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* | write_verilog: escape names that match SystemVerilog keywords.whitequark2019-01-271-0/+27
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* Add "write_edif -gndvccy"Clifford Wolf2019-01-171-5/+13
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Fix handling of $shiftx in Verilog back-endClifford Wolf2019-01-151-3/+6
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Fix typographical and grammatical errors and inconsistencies.whitequark2019-01-024-7/+7
| | | | | | | | | | | | The initial list of hits was generated with the codespell command below, and each hit was evaluated and fixed manually while taking context into consideration. DIRS="kernel/ frontends/ backends/ passes/ techlibs/" DIRS="${DIRS} libs/ezsat/ libs/subcircuit" codespell $DIRS -S *.o -L upto,iff,thru,synopsys,uint More hits were found by looking through comments and strings manually.
* Squelch a little more trailing whitespaceLarry Doolittle2018-12-291-3/+3
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* Minor style fixesClifford Wolf2018-12-182-1/+1
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Add btor ops for $mul, $div, $mod and $concatmakaimann2018-12-172-2/+38
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* write_verilog: handle the $shift cell.whitequark2018-12-161-0/+29
| | | | | | | | | | | | | | | | | | | | | | | | | | | The implementation corresponds to the following Verilog, which is lifted straight from simlib.v: module \\$shift (A, B, Y); parameter A_SIGNED = 0; parameter B_SIGNED = 0; parameter A_WIDTH = 0; parameter B_WIDTH = 0; parameter Y_WIDTH = 0; input [A_WIDTH-1:0] A; input [B_WIDTH-1:0] B; output [Y_WIDTH-1:0] Y; generate if (B_SIGNED) begin:BLOCK1 assign Y = $signed(B) < 0 ? A << -B : A >> B; end else begin:BLOCK2 assign Y = A >> B; end endgenerate endmodule
* Merge pull request #736 from whitequark/select_assert_listClifford Wolf2018-12-161-1/+1
|\ | | | | select: print selection if a -assert-* flag causes an error
| * write_verilog: add a missing newline.whitequark2018-12-161-1/+1
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* | Merge pull request #729 from whitequark/write_verilog_initialClifford Wolf2018-12-161-0/+2
|\ \ | | | | | | write_verilog: correctly map RTLIL `sync init`
| * | write_verilog: correctly map RTLIL `sync init`.whitequark2018-12-071-0/+2
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* | Add yosys-smtbmc support for btor witnessClifford Wolf2018-12-101-15/+100
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | Add "yosys-smtbmc --btorwit" skeletonClifford Wolf2018-12-081-1/+19
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | Fix btor init value handlingClifford Wolf2018-12-081-9/+13
|/ | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Add "write_aiger -I -O -B"Clifford Wolf2018-11-121-2/+36
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Merge pull request #693 from YosysHQ/rlimitClifford Wolf2018-11-071-8/+11
|\ | | | | improve rlimit handling in smtio.py
| * Limit stack size to 16 MB on DarwinClifford Wolf2018-11-071-1/+4
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * Fix for improved smtio.py rlimit codeClifford Wolf2018-11-061-1/+1
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * Improve stack rlimit code in smtio.pyClifford Wolf2018-11-061-8/+8
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | Run solver in non-incremental mode whem smtio.py is configured for ↵Clifford Wolf2018-11-061-3/+12
|/ | | | | | non-incremental solving Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Use conservative stack size for SMT2 on MacOSArjen Roodselaar2018-11-041-1/+6
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* Add proper error message for when smtbmc "append" failsClifford Wolf2018-11-041-2/+10
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Add support for signed $shift/$shiftx in smt2 back-endClifford Wolf2018-11-011-1/+3
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* adding offset info to memoriesrafaeltp2018-10-181-1/+1
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* adding offset info to memoriesrafaeltp2018-10-181-2/+3
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* Merge pull request #663 from aman-goel/masterClifford Wolf2018-10-171-32/+51
|\ | | | | Update to .smv backend
| * Minor updateAman Goel2018-10-151-1/+1
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| * Update to .smv backendAman Goel2018-10-011-33/+52
| | | | | | | | Splitting VAR and ASSIGN into IVAR, VAR, DEFINE and ASSIGN. This allows better handling by nuXmv for post-processing (since now only state variables are listed under VAR).
* | Add "write_edif -attrprop"Clifford Wolf2018-10-051-11/+28
|/ | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* added prefix to FDirection constants, fixing windows buildMiodrag Milanovic2018-09-211-11/+11
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* Fixed typo in "verilog_write" help messageacw12512018-09-181-3/+3
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* Add $lut support to Verilog back-endClifford Wolf2018-09-061-0/+13
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Remove unused functions.Jim Lawson2018-08-271-10/+0
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* Add support for module instances.Jim Lawson2018-08-231-17/+122
| | | | | | | Don't pad logical operands to one bit. Use operand width and signedness in $reduce_bool. Shift amounts are unsigned and shouldn't be padded. Group "is invalid" with the wire declaration, not its use (otherwise it is incorrectly wired to 0).
* Merge pull request #591 from hzeller/virtual-overrideClifford Wolf2018-08-1515-36/+36
|\ | | | | Consistent use of 'override' for virtual methods in derived classes.
| * Consistent use of 'override' for virtual methods in derived classes.Henner Zeller2018-07-2015-36/+36
| | | | | | | | | | | | | | | | | | o Not all derived methods were marked 'override', but it is a great feature of C++11 that we should make use of. o While at it: touched header files got a -*- c++ -*- for emacs to provide support for that language. o use YS_OVERRIDE for all override keywords (though we should probably use the plain keyword going forward now that C++11 is established)
* | Merge pull request #576 from cr1901/no-resourceClifford Wolf2018-08-151-9/+12
|\ \ | | | | | | Gate POSIX-only signals and resource module to only run on POSIX Pyth…
| * | Gate POSIX-only signals and resource module to only run on POSIX Python ↵William D. Jones2018-07-061-9/+12
| |/ | | | | | | implementations.
* | Fix use of signed integers in JSON back-endClifford Wolf2018-08-141-1/+3
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | Use `realpath` jpathy2018-08-061-1/+1
|/ | | Use `os.path.realpath` instead to make sure symlinks are followed. This is also required to work for nix package manager.
* Fix protobuf buildSergiusz Bazanski2018-06-201-1/+1
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* Add Protobuf backendSerge Bazanski2018-06-193-0/+380
| | | | Signed-off-by: Serge Bazanski <q3k@symbioticeda.com>
* Add $dlatch support to write_verilogClifford Wolf2018-04-221-0/+38
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Add "write_blif -inames -iattr"Clifford Wolf2018-04-151-22/+46
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Add smtio.py support for parsing SMT2 (_ bvX n) syntax for BitVec constantsClifford Wolf2018-04-041-0/+3
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Fixed -stbv handling in SMT2 back-endClifford Wolf2018-04-041-1/+1
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* Add smtio status msgs when --progress is inactiveClifford Wolf2018-03-291-2/+23
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
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