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* cxxrtl: Convert to Mem helpers.Marcelina Kościelnicka2021-07-121-206/+276
| | | | | This *only* does conversion, but doesn't add any new functionality — support for memory read port init/reset is still upcoming.
* Intersynth URLClaire Xenia Wolf2021-06-091-1/+1
| | | | Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
* Fixing old e-mail addresses and deadnamesClaire Xenia Wolf2021-06-0819-20/+20
| | | | | | | | s/((Claire|Xen|Xenia|Clifford)\s+)+(Wolf|Xen)\s+<(claire|clifford)@(symbioticeda.com|clifford.at|yosyshq.com)>/Claire Xenia Wolf <claire@yosyshq.com>/gi; s/((Nina|Nak|N\.)\s+)+Engelhardt\s+<nak@(symbioticeda.com|yosyshq.com)>/N. Engelhardt <nak@yosyshq.com>/gi; s/((David)\s+)+Shah\s+<(dave|david)@(symbioticeda.com|yosyshq.com|ds0.me)>/David Shah <dave@ds0.me>/gi; s/((Miodrag)\s+)+Milanovic\s+<(miodrag|micko)@(symbioticeda.com|yosyshq.com)>/Miodrag Milanovic <micko@yosyshq.com>/gi; s,https?://www.clifford.at/yosys/,http://yosyshq.net/yosys/,g;
* Make a few passes auto-call Mem::narrow instead of rejecting wide ports.Marcelina Kościelnicka2021-05-283-19/+6
| | | | | | This essentially adds wide port support for free in passes that don't have a usefully better way of handling wide ports than just breaking them up to narrow ports, avoiding "please run memory_narrow" annoyance.
* backends/verilog: Add support for memory read port reset and init value.Marcelina Kościelnicka2021-05-271-9/+81
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* backends/verilog: Add wide port support.Marcelina Kościelnicka2021-05-271-43/+88
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* backends/verilog: Try to preserve mem write port priorities.Marcelina Kościelnicka2021-05-261-32/+84
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* Reject wide ports in some passes that will never support them.Marcelina Kościelnicka2021-05-253-2/+21
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* backend/firrtl: Convert to use Mem helpers.Marcelina Kościelnicka2021-05-241-264/+88
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* btor: Use is_mem_cell in one more place.Marcelina Kościelnicka2021-05-231-1/+1
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* kernel/rtlil: Extract some helpers for checking memory cell types.Marcelina Kościelnicka2021-05-223-4/+4
| | | | | | There will soon be more (versioned) memory cells, so handle passes that only care if a cell is memory-related by a simple helper call instead of a hardcoded list.
* abc9: fix SCC issues (#2694)Eddie Hung2021-03-291-5/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * xilinx: add SCC test for DSP48E1 * xilinx: Gate DSP48E1 being a whitebox behind ALLOW_WHITEBOX_DSP48E1 Have a test that checks it works through ABC9 when enabled * abc9 to break SCCs using $__ABC9_SCC_BREAKER module * Add test * abc9_ops: remove refs to (* abc9_keep *) on wires * abc9_ops: do not bypass cells in an SCC * Add myself to CODEOWNERS for abc9* * Fix compile * abc9_ops: run -prep_hier before scc * Fix tests * Remove bug reference pending fix * abc9: fix for -prep_hier -dff * xaiger: restore PI handling * abc9_ops: -prep_xaiger sigmap * abc9_ops: -mark_scc -> -break_scc * abc9: eliminate hard-coded abc9.box from tests Also tidy up * Address review
* rtlil: Fix process memwr roundtrip.Marcelina Kościelnicka2021-03-231-1/+1
| | | | Fixes #2646 fallout.
* json: Improve the "processes in module" message a bit.Marcelina Kościelnicka2021-03-231-1/+1
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* json: Add support for memories.Marcelina Kościelnicka2021-03-151-0/+42
| | | | | | | | | | | | | | Previously, memories were silently discarded by the JSON backend, making round-tripping modules with them crash. Since there are already some users using JSON to implement custom external passes that use memories (and infer width/size from memory ports), let's fix this by just making JSON backend and frontend support memories as first-class objects. Processes are still not supported, and will now cause a hard error. Fixes #1908.
* Merge pull request #2642 from whitequark/cxxrtl-noproc-fixeswhitequark2021-03-111-17/+29
|\ | | | | CXXRTL: some -noproc fixes
| * cxxrtl: don't assert on edge sync rules tied to a constant.whitequark2021-03-071-0/+4
| | | | | | | | | | These are commonly the result of tying an async reset to an inactive level.
| * cxxrtl: allow `always` sync rules in debug_eval.whitequark2021-03-071-17/+25
| | | | | | | | | | These can be produced from `always @*` processes, if `-noproc` is used.
* | Replace assert in xaiger with more useful error messageDan Ravensloft2021-03-101-1/+2
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* | Add support for memory writes in processes.Marcelina Kościelnicka2021-03-081-3/+20
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* Merge pull request #2635 from whitequark/cxxrtl-memrd-async-addrwhitequark2021-03-051-1/+3
|\ | | | | cxxrtl: follow aliases to outlines when emitting $memrd.ADDR
| * cxxrtl: follow aliases to outlines when emitting $memrd.ADDR.whitequark2021-03-051-1/+3
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* | Merge pull request #2634 from whitequark/cxxrtl-debug-wire-typeswhitequark2021-03-051-0/+46
|\ \ | | | | | | cxxrtl: add pass debug flag to show assigned wire types
| * | cxxrtl: add pass debug flag to show assigned wire types.whitequark2021-03-051-0/+46
| |/ | | | | | | Refs #2543.
* / cxxrtl: don't crash on empty designs.whitequark2021-03-051-1/+1
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* btor, smt2, smv: Add a hint on how to deal with funny FF types.Marcelina Kościelnicka2021-02-253-3/+42
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* Merge pull request #2563 from whitequark/cxxrtl-msvcwhitequark2021-01-262-10/+10
|\ | | | | cxxrtl: do not use `->template` for non-dependent names
| * cxxrtl: do not use `->template` for non-dependent names.whitequark2021-01-262-10/+10
| | | | | | | | This breaks build on MSVC but not GCC/Clang.
* | Improves the previous commit with a more complete coverage of the casesIris Johnson2021-01-151-12/+12
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* | Handle sliced bits as clock inputs (fixes #2542)Iris Johnson2021-01-141-3/+11
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* add buffer option to spice backendPepijn de Vos2021-01-131-7/+15
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* cxxrtl: don't crash generating debug information for unused wires.whitequark2020-12-221-9/+10
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* cxxrtl: split processes into sync and case nodes.whitequark2020-12-221-11/+26
| | | | | | | | | | | Similar to the treatment of black boxes, splitting processes into two scheduling nodes adds sufficient freedom so that netlists with well-behaved processes (e.g. those emitted by nMigen) can immediately converge. Because processes are not emitted into edge-triggered regions, this approach has comparable performance to -O5 (without -noproc), which is substantially slower than -O6.
* cxxrtl: completely rewrite netlist layout code.whitequark2020-12-221-406/+569
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The exact shape of C++ code emitted by CXXRTL has a critical effect on performance, both compile-time and runtime. CXXRTL's performance greatly improved when it started localizing and inlining wires, not only because this assists the optimizer and register allocator, but also because inlining code into edge-triggered regions cuts the time spent in eval() by at least a factor of two. However, the logic of netlist layout has always been ad-hoc, fragile, and very hard to understand and modify. After commit ece25a45, which introduced outlining, the same logic started being applied to two distinct netlists at once instead of one, which barely worked. This commit does four major changes: * There is now a single unambiguous source of truth (per subgraph) for the layout of any emitted wire. * Netlist layout is now done entirely during analysis using well known graph algorithms; no graph operations happen when emitting. * Netlist layout now happens completely separately for eval() and debug_eval() subgraphs. * Unreachable (within subgraph scope) netlist nodes are now neither emitted nor considered for wire inlining decisions. The netlist layout code should also now closely match the described semantics. As a part of this large cleanup, it includes many miscellaneous improvements: * The "bare minimum" debug level introduced in commit dd6a761d was split into two levels; -g1 now emits debug information *only* for inputs and state wires, and -g2 now emits debug information for all public members. The old behavior matches -g2. This is done to avoid bloat on low optimization levels. * Debug aliases and inlined connections are now handled separately, and complex RHS never interferes with inlined connections. * Aliases to outlined wires now carry a pointer to the outline. * Cell sync outputs can now be emitted in debug_eval(). * Black box debug information now includes comb/sync driver flags. * The comment emitted for inlined cells is now accurate. * Debug information statistics now has less noise. * Netlist layout code is now much better documented. Due to more precise inlining decisions, unmodified (i.e. with no Yosys script being used) netlists now have much more logic inlined into edge-triggered regions. On Minerva SoC SRAM, this improves runtime by 20-25% across compilers and optimization levels. Due to more precise reachability analysis, much less C++ code is now emitted, especially at the maximum debug level. On Minerva SoC SRAM, this improves clang compile time by 30-50% depending on options. gcc is not affected.
* cxxrtl: simplify logic choosing wire type. NFCI.whitequark2020-12-211-19/+8
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* cxxrtl: clarify node use-def construction. NFCI.whitequark2020-12-211-18/+11
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* cxxrtl: fix typo.whitequark2020-12-211-2/+2
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* cxxrtl: speed up bit repeats (sign extends, etc).whitequark2020-12-212-5/+28
| | | | | On Minerva SoC SRAM, depending on the compiler, this change improves overall time by 4-7%.
* cxxrtl: speed up commits on clang.whitequark2020-12-211-3/+3
| | | | | | On Minerva SoC SRAM compiled with clang-11, this change cuts commit time in half (!) and overall time by 20%. When compiled with gcc-10, there is no difference.
* cxxrtl: use `static inline` instead of `inline` in the C API.whitequark2020-12-201-1/+1
| | | | | | In C, non-static inline functions require an implementation elsewhere (even though the body is right there in the header). It is basically never desirable to use those as opposed to static inline ones.
* cxxrtl: print names of cells inlined in connections.whitequark2020-12-151-1/+10
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* cxxrtl: disable optimization of debug_items().whitequark2020-12-152-3/+15
| | | | | | | | | | | | | | | | | | Implementing outlining has greatly increased the amount of debug information in a typical build, and consequently exposed performance issues in C++ compilers, which are similar for both GCC and Clang; the compile time of Minerva SoC SRAM increased almost twofold. Although one would expect the slowdown to be caused by the increased use of templates in `debug_eval()`, it is actually almost entirely attributable to optimizations and codegen for `debug_items()`. Fortunately, it is neither possible nor desirable to optimize `debug_items()`: in most cases it is called exactly once, and its body is a linear sequence of calls with unique arguments. This commit turns off optimizations for `debug_items()` on GCC and Clang, improving -Os compile time of Minerva SoC SRAM by ~40% (!)
* cxxrtl: make alias analysis outlining-aware.whitequark2020-12-151-38/+48
| | | | | | | | | | | | | | | | | | Before this commit, if a sequence of wires assigned in a chain would terminate on a cell, none of the wires would get marked as aliases, and typically all of the public wires would get outlined. The reason for this behavior is that alias analysis predates outlining and in fact runs before it. After this commit, alias analysis runs after outlining and considers outlined wires valid aliasees. More importantly, if the chained wires contain any valid aliasees, then all of the wires are aliased to the one that is topologically deepest. Aliased wires incur virtually no overhead for the VCD writer, unlike outlined wires that would otherwise take their place. On Minerva SoC SRAM, size of the full VCD dump is reduced by ~65%, and throughput is increased by ~55%.
* cxxrtl: add a "bare minimum" debug information level.whitequark2020-12-141-9/+17
| | | | | Useful to reduce overhead when no debug capabilities are necessary except for access to design state.
* cxxrtl: implement debug information outlining.whitequark2020-12-145-71/+278
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Aggressive wire localization and inlining is necessary for CXXRTL to achieve high performance. However, that comes with a cost: reduced debug information coverage. Previously, as a workaround, the `-Og` option could have been used to guarantee complete coverage, at a cost of a significant performance penalty. This commit introduces debug information outlining. The main eval() function is compiled with the user-specified optimization settings. In tandem, an auxiliary debug_eval() function, compiled from the same netlist, can be used to reconstruct the values of localized/inlined signals on demand. To the extent that it is possible, debug_eval() reuses the results of computations performed by eval(), only filling in the missing values. Benchmarking a representative design (Minerva SoC SRAM) shows that: * Switching from `-O4`/`-Og` to `-O6` reduces runtime by ~40%. * Switching from `-g1` to `-g2`, both used with `-O6`, increases compile time by ~25%. * Although `-g2` increases the resident size of generated modules, this has no effect on runtime. Because the impact of `-g2` is minimal and the benefits of having unconditional 100% debug information coverage (and the performance improvement as well) are major, this commit removes `-Og` and changes the defaults to `-O6 -g2`. We'll have our cake and eat it too!
* cxxrtl: rename "elision" to "inlining". NFC.whitequark2020-12-131-77/+77
| | | | | | | "Elision" in this context is an unusual and not very descriptive term whereas "inlining" is common and straightforward. Also, introducing "inlining" makes it easier to introduce its dual under the obvious name "outlining".
* cxxrtl: fix outdated comment. NFC.whitequark2020-12-131-2/+2
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* cxxrtl: use IdString::isPublic(). NFC.whitequark2020-12-131-4/+4
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* cxxrtl: don't overwrite buffered inputs.whitequark2020-12-112-25/+33
| | | | | | | | | | | | | | Before this commit, a cell's input was always assigned like: p_cell.p_input = (value...); If `p_input` is buffered (e.g. if the design is built at -O0), this is not correct. (In practice, this breaks clocking.) Unfortunately, the incorrect design was compiled without diagnostics because wire<> was move-assignable and also implicitly constructible from value<>. After this commit, cell inputs are no longer incorrectly assumed to always be unbuffered, and wires are not assignable from values.
* cxxrtl: allow customizing the root module path in the C API.whitequark2020-12-032-1/+20
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