| Commit message (Collapse) | Author | Age | Files | Lines |
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Now the nets are wired in reverse again because the netlister still uses zero-based indices.
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*to force renames on wide ports
*to choose array delimiters
*to choose up or downwards indices
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Chisel -> Firrtl -> Verilog -> Firrtl -> Verilog is successful for a
simple rocket-chip design.
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