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| author | Clifford Wolf <clifford@clifford.at> | 2017-02-14 12:49:35 +0100 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2017-02-14 12:49:35 +0100 |
| commit | 4e80ce97a8de55360a9aa5cb05c734fd4b0ba5c5 (patch) | |
| tree | a1024d0a6c2f2b7302ed7e3617371b3d564a1f5e /backends | |
| parent | 2a311c2c386ce173dca8c5e6e883a8f4f2d9ef00 (diff) | |
| download | yosys-4e80ce97a8de55360a9aa5cb05c734fd4b0ba5c5.tar.gz yosys-4e80ce97a8de55360a9aa5cb05c734fd4b0ba5c5.tar.bz2 yosys-4e80ce97a8de55360a9aa5cb05c734fd4b0ba5c5.zip | |
Add warning about x/z bits left unconnected in EDIF output
Diffstat (limited to 'backends')
| -rw-r--r-- | backends/edif/edif.cc | 7 |
1 files changed, 5 insertions, 2 deletions
diff --git a/backends/edif/edif.cc b/backends/edif/edif.cc index d16f18316..6414bc6e5 100644 --- a/backends/edif/edif.cc +++ b/backends/edif/edif.cc @@ -323,7 +323,10 @@ struct EdifBackend : public Backend { for (auto &p : cell->connections()) { RTLIL::SigSpec sig = sigmap(p.second); for (int i = 0; i < GetSize(sig); i++) - if (sig.size() == 1) + if (sig[i].wire == NULL && sig[i] != RTLIL::State::S0 && sig[i] != RTLIL::State::S1) + log_warning("Bit %d of cell port %s.%s.%s driven by %s will be left unconnected in EDIF output.\n", + i, log_id(module), log_id(cell), log_id(p.first), log_signal(sig[i])); + else if (sig.size() == 1) net_join_db[sig[i]].insert(stringf("(portRef %s (instanceRef %s))", EDIF_REF(p.first), EDIF_REF(cell->name))); else net_join_db[sig[i]].insert(stringf("(portRef (member %s %d) (instanceRef %s))", EDIF_REF(p.first), i, EDIF_REF(cell->name))); @@ -332,7 +335,7 @@ struct EdifBackend : public Backend { for (auto &it : net_join_db) { RTLIL::SigBit sig = it.first; if (sig.wire == NULL && sig != RTLIL::State::S0 && sig != RTLIL::State::S1) - continue; + log_abort(); std::string netname = log_signal(sig); for (size_t i = 0; i < netname.size(); i++) if (netname[i] == ' ' || netname[i] == '\\') |