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Author
Age
Files
Lines
*
Improvements in EDIF backend
Clifford Wolf
2013-09-17
2
-2
/
+41
*
Added additional options to BLIF backend
Clifford Wolf
2013-09-15
1
-15
/
+60
*
Added BLIF backend
Clifford Wolf
2013-09-15
2
-0
/
+245
*
A couple of small fixes in SPICE backend
Clifford Wolf
2013-09-15
1
-6
/
+18
*
Added spice testbench to techlibs/cmos
Clifford Wolf
2013-09-14
1
-3
/
+0
*
Added spice backend
Clifford Wolf
2013-09-14
2
-0
/
+228
*
Merge branch 'master' of github.com:cliffordwolf/yosys
Clifford Wolf
2013-09-03
1
-8
/
+31
|
\
|
*
Encode large (>32 bits) parameters as hex string in edif backend
Clifford Wolf
2013-08-28
1
-3
/
+16
|
*
Improved edif backend
Clifford Wolf
2013-08-27
1
-8
/
+18
*
|
Added -selected option to various backends
Clifford Wolf
2013-09-03
3
-9
/
+58
|
/
*
More explicit integer output in verilog backend
Clifford Wolf
2013-08-22
1
-2
/
+2
*
Added correct encoding of identifiers in EDIF backend
Clifford Wolf
2013-08-22
1
-13
/
+61
*
Added edif backend (still under construction)
Clifford Wolf
2013-08-22
2
-0
/
+202
*
Fixed generation of newlines in "dump" output
Clifford Wolf
2013-06-10
1
-3
/
+4
*
Added "dump" command (part ilang backend)
Clifford Wolf
2013-06-02
2
-13
/
+103
*
Implemented proper handling of stub placeholder modules
Clifford Wolf
2013-03-28
1
-6
/
+18
*
Added -notypes option to intersynth backend
Clifford Wolf
2013-03-24
1
-7
/
+18
*
Fixed gcc build (intersynth backend)
Clifford Wolf
2013-03-23
1
-14
/
+14
*
Various improvements in intersynth backend
Clifford Wolf
2013-03-23
1
-9
/
+56
*
Added intersynth backend
Clifford Wolf
2013-03-23
2
-0
/
+141
*
Avoid verilog-2k in verilog backend
Clifford Wolf
2013-03-21
1
-0
/
+17
*
More support code for $sr cells
Clifford Wolf
2013-03-14
1
-1
/
+29
*
Fixed a gcc compiler warning [-Wparentheses]
Clifford Wolf
2013-03-03
1
-1
/
+2
*
Added more help messages
Clifford Wolf
2013-03-01
3
-3
/
+59
*
initial import
Clifford Wolf
2013-01-05
8
-0
/
+1615