Merge branch 'master' of github.com:cliffordwolf/yosys

1 files changed, 31 insertions, 8 deletions

diff --git a/backends/edif/edif.cc b/backends/edif/edif.cc
index a3231107f..944e576a5 100644
--- a/backends/edif/edif.cc
+++ b/backends/edif/edif.cc
@@ -196,21 +196,44 @@ struct EdifBackend : public Backend {
 					dir = "INPUT";
 				else if (!wire->port_input)
 					dir = "OUTPUT";
-				for (int i = 0; i < wire->width; i++) {
-					std::string portname = wire->width > 1 ? stringf("%s[%d]", RTLIL::id2cstr(wire->name),
-							i+wire->start_offset) : RTLIL::id2cstr(wire->name);
-					fprintf(f, "          (port %s (direction %s))\n", edif_names(portname).c_str(), dir);
-					RTLIL::SigSpec sig = sigmap(RTLIL::SigSpec(wire, 1, i));
-					net_join_db[sig].insert(stringf("(portRef %s)", edif_names(portname).c_str()));
+				if (wire->width == 1) {
+					fprintf(f, "          (port %s (direction %s))\n", EDIF_NAME(wire->name), dir);
+					RTLIL::SigSpec sig = sigmap(RTLIL::SigSpec(wire));
+					net_join_db[sig].insert(stringf("(portRef %s)", EDIF_NAME(wire->name)));
+				} else {
+					fprintf(f, "          (port (array %s %d) (direction %s))\n", EDIF_NAME(wire->name), wire->width, dir);
+					for (int i = 0; i < wire->width; i++) {
+						RTLIL::SigSpec sig = sigmap(RTLIL::SigSpec(wire, 1, i));
+						net_join_db[sig].insert(stringf("(portRef (member %s %d))", EDIF_NAME(wire->name), i));
+					}
 				}
 			}
 			fprintf(f, "        )\n");
 			fprintf(f, "        (contents\n");
 			for (auto &cell_it : module->cells) {
 				RTLIL::Cell *cell = cell_it.second;
-				fprintf(f, "          (instance %s (viewRef VIEW_NETLIST (cellRef %s%s)))\n",
-						EDIF_NAME(cell->name), EDIF_NAME(cell->type),
+				fprintf(f, "          (instance %s\n", EDIF_NAME(cell->name));
+				fprintf(f, "            (viewRef VIEW_NETLIST (cellRef %s%s))", EDIF_NAME(cell->type),
 						lib_cell_ports.count(cell->type) > 0 ? " (libraryRef LIB)" : "");
+				for (auto &p : cell->parameters)
+					if (!p.second.str.empty())
+						fprintf(f, "\n            (property %s (string \"%s\"))", EDIF_NAME(p.first), p.second.str.c_str());
+					else if (p.second.bits.size() <= 32 && RTLIL::SigSpec(p.second).is_fully_def())
+						fprintf(f, "\n            (property %s (integer %u))", EDIF_NAME(p.first), p.second.as_int());
+					else {
+						std::string hex_string = "";
+						for (size_t i = 0; i < p.second.bits.size(); i += 4) {
+							int digit_value = 0;
+							if (i+0 < p.second.bits.size() && p.second.bits.at(i+0) == RTLIL::State::S1) digit_value += 1;
+							if (i+1 < p.second.bits.size() && p.second.bits.at(i+1) == RTLIL::State::S1) digit_value += 2;
+							if (i+2 < p.second.bits.size() && p.second.bits.at(i+2) == RTLIL::State::S1) digit_value += 3;
+							if (i+3 < p.second.bits.size() && p.second.bits.at(i+3) == RTLIL::State::S1) digit_value += 4;
+							char digit_str[2] = { "0123456789abcdef"[digit_value], 0 };
+							hex_string = std::string(digit_str) + hex_string;
+						}
+						fprintf(f, "\n            (property %s (string \"%s\"))", EDIF_NAME(p.first), hex_string.c_str());
+					}
+				fprintf(f, ")\n");
 				for (auto &p : cell->connections) {
 					RTLIL::SigSpec sig = sigmap(p.second);
 					sig.expand();