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* Bugfixes in writing of memories as VerilogClifford Wolf2015-09-251-7/+8
* Added "yosys-smt2-wire" tag support to smt2 back-endClifford Wolf2015-08-311-0/+2
* Fixed generation of smt2 concat statementsClifford Wolf2015-08-151-3/+5
* Another block of spelling fixesLarry Doolittle2015-08-143-4/+4
* Re-created command-reference-manual.tex, copied some doc fixes to online helpClifford Wolf2015-08-141-3/+3
* Spell check (by Larry Doolittle)Clifford Wolf2015-08-142-3/+3
* Added "write_smt2 -regs"Clifford Wolf2015-08-121-7/+36
* Added SMV back-end 'test_cells.sh' scriptClifford Wolf2015-08-121-0/+33
* Use MEMID as name for $mem cellClifford Wolf2015-08-091-1/+6
* Remove some very strange whitespace in btor.cc (by Larry Doolittle)Clifford Wolf2015-08-051-7/+7
* Bugfix in SMV back-end for partially unassigned wiresClifford Wolf2015-08-051-4/+16
* Added $assert support to SMV back-endClifford Wolf2015-08-041-4/+21
* Improvements in BLIF back-endClifford Wolf2015-07-291-5/+84
* Fixed trailing whitespacesClifford Wolf2015-07-0213-114/+114
* Added init support to SMV back-endClifford Wolf2015-06-191-1/+3
* Progress in SMV back-endClifford Wolf2015-06-191-64/+115
* Progress in SMV back-endClifford Wolf2015-06-191-13/+59
* Progress in SMV back-endClifford Wolf2015-06-181-24/+94
* Progress in SMV back-endClifford Wolf2015-06-171-11/+72
* Progress in SMV back-endClifford Wolf2015-06-171-11/+64
* Progress in SMV back-endClifford Wolf2015-06-161-3/+46
* Progress in SMV back-endClifford Wolf2015-06-151-2/+95
* Progress in SMV back-endClifford Wolf2015-06-151-7/+85
* Added "write_smv" skeletonClifford Wolf2015-06-152-0/+261
* Removed debug code from write_smt2Clifford Wolf2015-06-141-2/+0
* Added write_smt2 -memClifford Wolf2015-06-141-80/+157
* Fixed cstr_buf for std::string with small string optimizationClifford Wolf2015-06-112-2/+2
* Improvements in cellaigs.cc and "json -aig"Clifford Wolf2015-06-111-6/+63
* AigMaker refactoringClifford Wolf2015-06-101-1/+1
* Added "json -aig"Clifford Wolf2015-06-101-9/+63
* $mem cell in verilog backend : grouped writes by clockluke whittlesey2015-06-081-54/+108
* Bug fix in $mem verilog backend + changed tests/bram flow of make test.luke whittlesey2015-06-041-14/+16
* Improvements in BLIF front-endClifford Wolf2015-05-241-0/+1
* Some fixes for $mem in verilog back-endClifford Wolf2015-05-201-19/+23
* Merge pull request #63 from wluker/verilog-backend-memClifford Wolf2015-05-111-1/+2
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| * Fixed bug in $mem cell verilog code generation.luke whittlesey2015-05-111-11/+12
* | Disabled broken $mem support in verilog backendClifford Wolf2015-05-101-11/+11
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* Made changes recommended by Clifford Wolf ...luke whittlesey2015-05-101-22/+11
* Verilog backend for $mem cells should now be able to handle differentluke whittlesey2015-05-081-50/+105
* Added support for $mem cells in the verilog backend.luke whittlesey2015-05-071-1/+120
* Minor fixes in handling of "init" attributeClifford Wolf2015-04-091-7/+7
* Removed "techmap -share_map" (use "-map +/filename" instead)Clifford Wolf2015-04-081-1/+1
* Added "port_directions" to write_json outputClifford Wolf2015-04-061-0/+20
* Added "init" attribute support to verilog backendClifford Wolf2015-04-041-0/+5
* Update READMEAhmed Irfan2015-04-031-1/+1
* Delete btor.ysAhmed Irfan2015-04-031-18/+0
* Update READMEAhmed Irfan2015-04-031-1/+1
* separated memory next from write cellAhmed Irfan2015-04-031-7/+55
* Added Verilog backend $dffsr supportClifford Wolf2015-03-181-1/+51
* Documentation for JSON format, added attributesClifford Wolf2015-03-061-16/+156
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