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authorClifford Wolf <clifford@clifford.at>2015-08-14 11:27:19 +0200
committerClifford Wolf <clifford@clifford.at>2015-08-14 11:27:19 +0200
commit03500748192dc93583c0e0f95640865603650714 (patch)
treeca2a7fda2451656a9be78763ac741d6e14253c3d /backends
parent84bf862f7c58c2b69babf043ff5032f924a3ee4d (diff)
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Re-created command-reference-manual.tex, copied some doc fixes to online help
Diffstat (limited to 'backends')
-rw-r--r--backends/verilog/verilog_backend.cc6
1 files changed, 3 insertions, 3 deletions
diff --git a/backends/verilog/verilog_backend.cc b/backends/verilog/verilog_backend.cc
index e6a86a16a..28c54ce0b 100644
--- a/backends/verilog/verilog_backend.cc
+++ b/backends/verilog/verilog_backend.cc
@@ -1315,14 +1315,14 @@ void dump_module(std::ostream &f, std::string indent, RTLIL::Module *module)
}
struct VerilogBackend : public Backend {
- VerilogBackend() : Backend("verilog", "write design to verilog file") { }
+ VerilogBackend() : Backend("verilog", "write design to Verilog file") { }
virtual void help()
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
log(" write_verilog [options] [filename]\n");
log("\n");
- log("Write the current design to a verilog file.\n");
+ log("Write the current design to a Verilog file.\n");
log("\n");
log(" -norename\n");
log(" without this option all internal object names (the ones with a dollar\n");
@@ -1336,7 +1336,7 @@ struct VerilogBackend : public Backend {
log(" with this option attributes are included as comments in the output\n");
log("\n");
log(" -noexpr\n");
- log(" without this option all internal cells are converted to verilog\n");
+ log(" without this option all internal cells are converted to Verilog\n");
log(" expressions.\n");
log("\n");
log(" -blackboxes\n");