iCE40/yosys - [no description]

	Commit message (Expand)	Author	Age	Files	Lines
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*	cxxrtl: order -On levels as localize, elide instead of the reverse.	whitequark	2020-06-09	1	-8/+8
*	cxxrtl: factor out -noproc/-noflatten from -O.	whitequark	2020-06-09	1	-17/+36
*	cxxrtl: fix two buggy split_by functions.	whitequark	2020-06-09	2	-14/+16
*	Merge pull request #2126 from whitequark/cxxrtl-non-ext-logic-ops	whitequark	2020-06-09	2	-64/+35
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\| *	cxxrtl: ignore cell input signedness when it is irrelevant.	whitequark	2020-06-09	2	-64/+35
* \|	cxxrtl: add missing namespace.	whitequark	2020-06-09	1	-2/+2
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*	cxxrtl: fix format of hdlnames.	whitequark	2020-06-08	1	-1/+1
*	cxxrtl: don't check immutable values for changes in VCD writer.	whitequark	2020-06-08	1	-4/+10
*	cxxrtl: emit debug information for constant wires.	whitequark	2020-06-08	3	-17/+44
*	cxxrtl: track aliases in VCD writer.	whitequark	2020-06-08	1	-10/+14
*	cxxrtl: emit debug information for alias wires.	whitequark	2020-06-08	1	-3/+55
*	cxxrtl: fix typo in comment. NFC.	whitequark	2020-06-08	1	-4/+4
*	cxxrtl: minor debug-related improvements.	whitequark	2020-06-08	1	-2/+3
*	cxxrtl: rename cxxrtl.cc→cxxrtl_backend.cc.	whitequark	2020-06-07	2	-1/+1
*	cxxrtl: add a C API for writing VCD dumps.	whitequark	2020-06-07	5	-2/+204
*	cxxrtl: only write VCD values that were actually updated.	whitequark	2020-06-07	1	-10/+30
*	cxxrtl: add a VCD writer using debug information.	whitequark	2020-06-07	1	-0/+194
*	cxxrtl: add a C API for driving and introspecting designs.	whitequark	2020-06-06	4	-29/+291
*	cxxrtl: generate debug information for non-localized public wires.	whitequark	2020-06-06	2	-2/+131
*	Merge pull request #2110 from BracketMaster/master	whitequark	2020-06-06	1	-1/+1
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\| *	more reasonable numbers for memory	Yehowshua Immanuel	2020-06-04	1	-1/+1
\| *	MacOS has even stricter stack limits in catalina.	Yehowshua Immanuel	2020-06-04	1	-1/+1
* \|	Merge pull request #2113 from whitequark/cxxrtl-fix-sshr	whitequark	2020-06-05	1	-1/+1
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\| * \|	cxxrtl: fix implementation of $sshr cell.	whitequark	2020-06-05	1	-1/+1
* \| \|	Merge pull request #2109 from nakengelhardt/btor_internal_names	N. Engelhardt	2020-06-05	1	-5/+5
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\| * \|	btor backend: make not printing internal names default	N. Engelhardt	2020-06-04	1	-5/+5
* \| \|	Merge pull request #2077 from YosysHQ/eddie/abc9_dff_improve	Eddie Hung	2020-06-04	1	-28/+22
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\| * \|	xaiger: cleanup	Eddie Hung	2020-05-25	1	-28/+22
* \| \|	Add printf format attributes to btorf/infof helper functions	Claire Wolf	2020-06-04	1	-3/+3
* \| \|	btor backend: add option to not include internal names	N. Engelhardt	2020-06-04	1	-33/+42
* \| \|	Merge pull request #2006 from jersey99/signed-in-rtlil-wire	whitequark	2020-06-04	2	-0/+6
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\| * \| \|	Preserve 'signed'-ness of a verilog wire through RTLIL	Vamsi K Vytla	2020-04-27	2	-0/+6
* \| \| \|	Merge pull request #2082 from YosysHQ/eddie/abc9_scc_fixes	Eddie Hung	2020-06-03	1	-1/+1
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\| * \| \|	xaiger: promote abc9_keep wires	Eddie Hung	2020-05-25	1	-1/+1
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* \| \|	Merge pull request #2018 from boqwxp/qbfsat-timeout	clairexen	2020-05-30	2	-5/+31
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\| * \| \|	smtbmc: Remove superfluous `yosys-smt2-timeout` file macro.	Alberto Gonzalez	2020-05-29	1	-4/+0
\| * \| \|	smtbmc and qbfsat: Add timeout option to set solver timeouts for Z3, Yices, a...	Alberto Gonzalez	2020-05-25	2	-5/+35
* \| \| \|	Merge pull request #1885 from Xiretza/mod-rem-cells	clairexen	2020-05-29	7	-9/+116
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\| * \| \| \|	Add flooring division operator	Xiretza	2020-05-28	3	-3/+58
\| * \| \| \|	Add flooring modulo operator	Xiretza	2020-05-28	7	-9/+61
* \| \| \| \|	Merge pull request #2016 from boqwxp/qbfsat-yices	clairexen	2020-05-29	1	-1/+5
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\| * \| \|	qbfsat: Move SMT2 info statements back to the top of the file.	Alberto Gonzalez	2020-05-25	1	-3/+3
\| * \| \|	qbfsat: Add `-solver` option and allow choice of Z3 or Yices, making Yices th...	Alberto Gonzalez	2020-05-25	1	-3/+7
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* \| \|	Merge pull request #2031 from epfl-vlsc/master	whitequark	2020-05-28	1	-1/+40
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\| * \| \|	Formatting fixes	Sahand Kashani	2020-05-06	1	-14/+7
\| * \| \|	Add extmodule support to firrtl backend	Sahand Kashani	2020-05-06	1	-1/+47
* \| \| \|	Merge pull request #2063 from boqwxp/techmapped-firrtl	whitequark	2020-05-28	1	-10/+12
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\| * \| \| \|	firrtl: Accept techmapped cell types in FIRRTL backend.	Alberto Gonzalez	2020-05-17	1	-10/+12
* \| \| \| \|	cxxrtl: make logging a little bit nicer.	whitequark	2020-05-26	1	-2/+10
* \| \| \| \|	cxxrtl: add missing parts of commit 281c9685.	whitequark	2020-05-26	1	-5/+3
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