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author | Eddie Hung <eddie@fpgeh.com> | 2020-06-03 17:35:46 -0700 |
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committer | GitHub <noreply@github.com> | 2020-06-03 17:35:46 -0700 |
commit | 45cd323055270ff414419ddf8a9b5d08f40628b5 (patch) | |
tree | dca3058ce1f8bfa3a030716d40abf662d6733c0f /backends | |
parent | 46ed0db2ec883a4ce330c81f321511e36e35c0b3 (diff) | |
parent | 8a11019d382f3eb5a8d95ce64511a1dcbbe2acfe (diff) | |
download | yosys-45cd323055270ff414419ddf8a9b5d08f40628b5.tar.gz yosys-45cd323055270ff414419ddf8a9b5d08f40628b5.tar.bz2 yosys-45cd323055270ff414419ddf8a9b5d08f40628b5.zip |
Merge pull request #2082 from YosysHQ/eddie/abc9_scc_fixes
abc9: fixes around handling combinatorial loops
Diffstat (limited to 'backends')
-rw-r--r-- | backends/aiger/xaiger.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/backends/aiger/xaiger.cc b/backends/aiger/xaiger.cc index 6b910eecd..4a8f54c4d 100644 --- a/backends/aiger/xaiger.cc +++ b/backends/aiger/xaiger.cc @@ -156,7 +156,7 @@ struct XAigerWriter // promote keep wires for (auto wire : module->wires()) - if (wire->get_bool_attribute(ID::keep)) + if (wire->get_bool_attribute(ID::keep) || wire->get_bool_attribute(ID::abc9_keep)) sigmap.add(wire); for (auto wire : module->wires()) { |