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* Fixed hex string generation bug in edif backendClifford Wolf2013-10-271-4/+4
* Added support for complex set-reset flip-flops in proc_dffClifford Wolf2013-10-241-1/+6
* Fixed handling of boolean attributes (backends)Clifford Wolf2013-10-246-10/+10
* Fixed handling of boolean attributes (kernel)Clifford Wolf2013-10-241-4/+4
* Added $_SR_[PN][PN]_, $_DFFSR_[PN][PN][PN]_, $_DLATCH_[PN]_Clifford Wolf2013-10-181-0/+1
* Added $sr, $dffsr and $dlatch cell typesClifford Wolf2013-10-181-28/+1
* Added -buf, -true and -false options to blif backendClifford Wolf2013-10-171-2/+40
* Improvements in EDIF backendClifford Wolf2013-09-172-2/+41
* Added additional options to BLIF backendClifford Wolf2013-09-151-15/+60
* Added BLIF backendClifford Wolf2013-09-152-0/+245
* A couple of small fixes in SPICE backendClifford Wolf2013-09-151-6/+18
* Added spice testbench to techlibs/cmosClifford Wolf2013-09-141-3/+0
* Added spice backendClifford Wolf2013-09-142-0/+228
* Merge branch 'master' of github.com:cliffordwolf/yosysClifford Wolf2013-09-031-8/+31
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| * Encode large (>32 bits) parameters as hex string in edif backendClifford Wolf2013-08-281-3/+16
| * Improved edif backendClifford Wolf2013-08-271-8/+18
* | Added -selected option to various backendsClifford Wolf2013-09-033-9/+58
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* More explicit integer output in verilog backendClifford Wolf2013-08-221-2/+2
* Added correct encoding of identifiers in EDIF backendClifford Wolf2013-08-221-13/+61
* Added edif backend (still under construction)Clifford Wolf2013-08-222-0/+202
* Fixed generation of newlines in "dump" outputClifford Wolf2013-06-101-3/+4
* Added "dump" command (part ilang backend)Clifford Wolf2013-06-022-13/+103
* Implemented proper handling of stub placeholder modulesClifford Wolf2013-03-281-6/+18
* Added -notypes option to intersynth backendClifford Wolf2013-03-241-7/+18
* Fixed gcc build (intersynth backend)Clifford Wolf2013-03-231-14/+14
* Various improvements in intersynth backendClifford Wolf2013-03-231-9/+56
* Added intersynth backendClifford Wolf2013-03-232-0/+141
* Avoid verilog-2k in verilog backendClifford Wolf2013-03-211-0/+17
* More support code for $sr cellsClifford Wolf2013-03-141-1/+29
* Fixed a gcc compiler warning [-Wparentheses]Clifford Wolf2013-03-031-1/+2
* Added more help messagesClifford Wolf2013-03-013-3/+59
* initial importClifford Wolf2013-01-058-0/+1615