aboutsummaryrefslogtreecommitdiffstats
path: root/backends
Commit message (Collapse)AuthorAgeFilesLines
...
* Split module ports, 20 per lineMiodrag Milanovic2021-10-091-0/+2
|
* Hook up $aldff support in various passes.Marcelina Kościelnicka2021-10-024-4/+19
|
* kernel/ff: Refactor FfData to enable FFs with async load.Marcelina Kościelnicka2021-10-021-43/+70
| | | | | | | | | | - *_en is split into *_ce (clock enable) and *_aload (async load aka latch gate enable), so both can be present at once - has_d is removed - has_gclk is added (to have a clear marker for $ff) - d_is_const and val_d leftovers are removed - async2sync, clk2fflogic, opt_dff are updated to operate correctly on FFs with async load
* Add optimization to rtlil back-end for all-x parameter valuesClaire Xenia Wolf2021-09-271-9/+13
| | | | Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
* Fix protobuf backend build dependenciesthe6p4c2021-09-171-0/+2
| | | | | | | backends/protobuf/protobuf.cc depends on the source and header files generated by protoc, but this dependency wasn't explicitly declared. Add a rule to the Makefile to fix intermittent build failures when the protobuf header/source file isn't built before protobuf.cc.
* yosys-smtbmc: Fix reused loop variable.Marcelina Kościelnicka2021-09-101-4/+4
| | | | Fixes #2999.
* kernel/mem: Introduce transparency masks.Marcelina Kościelnicka2021-08-112-27/+30
|
* backend/verilog: Add alternate mode for transparent read port output.Marcelina Kościelnicka2021-08-011-1/+71
| | | | | | This mode will be used whenever read port cannot be handled in the "extract address register" way, ie. whenever it has enable, reset, init functionality or (in the future) mixed transparency mask.
* backends/verilog: Support meminit with mask.Marcelina Kościelnicka2021-07-281-3/+18
|
* Merge pull request #2885 from whitequark/cxxrtl-fix-2883whitequark2021-07-201-2/+8
|\ | | | | cxxrtl: treat wires with multiple defs as not inlinable
| * cxxrtl: treat wires with multiple defs as not inlinable.whitequark2021-07-201-2/+8
| | | | | | | | Fixes #2883.
* | cxxrtl: treat assignable internal wires used only for debug as locals.whitequark2021-07-201-10/+12
|/ | | | | | This issue was introduced in commit 4aa65f40 while fixing #2739. Fixes #2882.
* cxxrtl: escape colon in variable names in VCD writer.whitequark2021-07-191-1/+14
| | | | | | | | | | | | The following VCD file crashes GTKWave's VCD loader: $var wire 1 ! x:1 $end $enddefinitions $end In practice, a colon can be a part of a variable name that is translated from a Verilog function, something like: update$func$.../hdl/hazard3_csr.v:350$2534.$result
* cxxrtl: add debug_item::{get,set}.whitequark2021-07-181-0/+16
| | | | Fixes #2877.
* cxxrtl: treat internal wires used only for debug as constants.whitequark2021-07-171-0/+6
| | | | Fixes #2739 (again).
* Merge pull request #2874 from whitequark/cxxrtl-fix-2589whitequark2021-07-161-9/+6
|\ | | | | cxxrtl: run hierarchy pass regardless of (*top*) attribute presence
| * cxxrtl: run hierarchy pass regardless of (*top*) attribute presence.whitequark2021-07-161-9/+6
| | | | | | | | | | | | | | The hierarchy pass does a lot more than just finding the top module, mainly resolving implicit (positional, wildcard) module connections. Fixes #2589.
* | Merge pull request #2873 from whitequark/cxxrtl-fix-2500whitequark2021-07-161-3/+3
|\ \ | | | | | | cxxrtl: emit debug items for unused public wires
| * | cxxrtl: emit debug items for unused public wires.whitequark2021-07-161-3/+3
| |/ | | | | | | | | | | This greatly improves debug information coverage. Fixes #2500.
* / cxxrtl: don't expect user cell inputs to be wires.whitequark2021-07-161-2/+2
|/ | | | | | Ports can be connected to constants, too. (Usually resets.) Fixes #2521.
* cxxrtl: don't mark buffered internal wires as UNUSED for debug.whitequark2021-07-161-1/+1
| | | | | | | | | | Public wires may alias buffered internal wires, so keep BUFFERED wires in debug information even if they are private. Debug items are only created for public wires, so this does not otherwise affect how debug information is emitted. Fixes #2540. Fixes #2841.
* cxxrtl: mark dead local wires as unused even with inlining disabled.whitequark2021-07-151-4/+6
| | | | Fixes #2739.
* kernel/mem: Add a coalesce_inits helper.Marcelina Kościelnicka2021-07-131-1/+5
| | | | | | | While this helper is already useful to squash sequential initializations into one in cxxrtl, its main purpose is to squash overlapping masked memory initializations (when they land) and avoid having to deal with them in cxxrtl runtime.
* Add support for the Bitwuzla solverGCHQDeveloper5602021-07-121-5/+5
|
* cxxrtl: Support memory writes in processes.Marcelina Kościelnicka2021-07-121-6/+55
|
* cxxrtl: Add support for memory read port reset.Marcelina Kościelnicka2021-07-121-1/+41
|
* cxxrtl: Add support for mem read port initial data.Marcelina Kościelnicka2021-07-121-4/+22
|
* cxxrtl: Convert to Mem helpers.Marcelina Kościelnicka2021-07-121-206/+276
| | | | | This *only* does conversion, but doesn't add any new functionality — support for memory read port init/reset is still upcoming.
* Intersynth URLClaire Xenia Wolf2021-06-091-1/+1
| | | | Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
* Fixing old e-mail addresses and deadnamesClaire Xenia Wolf2021-06-0819-20/+20
| | | | | | | | s/((Claire|Xen|Xenia|Clifford)\s+)+(Wolf|Xen)\s+<(claire|clifford)@(symbioticeda.com|clifford.at|yosyshq.com)>/Claire Xenia Wolf <claire@yosyshq.com>/gi; s/((Nina|Nak|N\.)\s+)+Engelhardt\s+<nak@(symbioticeda.com|yosyshq.com)>/N. Engelhardt <nak@yosyshq.com>/gi; s/((David)\s+)+Shah\s+<(dave|david)@(symbioticeda.com|yosyshq.com|ds0.me)>/David Shah <dave@ds0.me>/gi; s/((Miodrag)\s+)+Milanovic\s+<(miodrag|micko)@(symbioticeda.com|yosyshq.com)>/Miodrag Milanovic <micko@yosyshq.com>/gi; s,https?://www.clifford.at/yosys/,http://yosyshq.net/yosys/,g;
* Make a few passes auto-call Mem::narrow instead of rejecting wide ports.Marcelina Kościelnicka2021-05-283-19/+6
| | | | | | This essentially adds wide port support for free in passes that don't have a usefully better way of handling wide ports than just breaking them up to narrow ports, avoiding "please run memory_narrow" annoyance.
* backends/verilog: Add support for memory read port reset and init value.Marcelina Kościelnicka2021-05-271-9/+81
|
* backends/verilog: Add wide port support.Marcelina Kościelnicka2021-05-271-43/+88
|
* backends/verilog: Try to preserve mem write port priorities.Marcelina Kościelnicka2021-05-261-32/+84
|
* Reject wide ports in some passes that will never support them.Marcelina Kościelnicka2021-05-253-2/+21
|
* backend/firrtl: Convert to use Mem helpers.Marcelina Kościelnicka2021-05-241-264/+88
|
* btor: Use is_mem_cell in one more place.Marcelina Kościelnicka2021-05-231-1/+1
|
* kernel/rtlil: Extract some helpers for checking memory cell types.Marcelina Kościelnicka2021-05-223-4/+4
| | | | | | There will soon be more (versioned) memory cells, so handle passes that only care if a cell is memory-related by a simple helper call instead of a hardcoded list.
* abc9: fix SCC issues (#2694)Eddie Hung2021-03-291-5/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * xilinx: add SCC test for DSP48E1 * xilinx: Gate DSP48E1 being a whitebox behind ALLOW_WHITEBOX_DSP48E1 Have a test that checks it works through ABC9 when enabled * abc9 to break SCCs using $__ABC9_SCC_BREAKER module * Add test * abc9_ops: remove refs to (* abc9_keep *) on wires * abc9_ops: do not bypass cells in an SCC * Add myself to CODEOWNERS for abc9* * Fix compile * abc9_ops: run -prep_hier before scc * Fix tests * Remove bug reference pending fix * abc9: fix for -prep_hier -dff * xaiger: restore PI handling * abc9_ops: -prep_xaiger sigmap * abc9_ops: -mark_scc -> -break_scc * abc9: eliminate hard-coded abc9.box from tests Also tidy up * Address review
* rtlil: Fix process memwr roundtrip.Marcelina Kościelnicka2021-03-231-1/+1
| | | | Fixes #2646 fallout.
* json: Improve the "processes in module" message a bit.Marcelina Kościelnicka2021-03-231-1/+1
|
* json: Add support for memories.Marcelina Kościelnicka2021-03-151-0/+42
| | | | | | | | | | | | | | Previously, memories were silently discarded by the JSON backend, making round-tripping modules with them crash. Since there are already some users using JSON to implement custom external passes that use memories (and infer width/size from memory ports), let's fix this by just making JSON backend and frontend support memories as first-class objects. Processes are still not supported, and will now cause a hard error. Fixes #1908.
* Merge pull request #2642 from whitequark/cxxrtl-noproc-fixeswhitequark2021-03-111-17/+29
|\ | | | | CXXRTL: some -noproc fixes
| * cxxrtl: don't assert on edge sync rules tied to a constant.whitequark2021-03-071-0/+4
| | | | | | | | | | These are commonly the result of tying an async reset to an inactive level.
| * cxxrtl: allow `always` sync rules in debug_eval.whitequark2021-03-071-17/+25
| | | | | | | | | | These can be produced from `always @*` processes, if `-noproc` is used.
* | Replace assert in xaiger with more useful error messageDan Ravensloft2021-03-101-1/+2
| |
* | Add support for memory writes in processes.Marcelina Kościelnicka2021-03-081-3/+20
|/
* Merge pull request #2635 from whitequark/cxxrtl-memrd-async-addrwhitequark2021-03-051-1/+3
|\ | | | | cxxrtl: follow aliases to outlines when emitting $memrd.ADDR
| * cxxrtl: follow aliases to outlines when emitting $memrd.ADDR.whitequark2021-03-051-1/+3
| |
* | Merge pull request #2634 from whitequark/cxxrtl-debug-wire-typeswhitequark2021-03-051-0/+46
|\ \ | | | | | | cxxrtl: add pass debug flag to show assigned wire types
generated by cgit v1.2.3 (git 2.25.1) at 2024-07-12 03:36:18 +0000