| Commit message (Collapse) | Author | Age | Files | Lines | ||
|---|---|---|---|---|---|---|
| ... | ||||||
| | | * | | Use State::S{0,1} | Eddie Hung | 2019-08-06 | 3 | -6/+6 | |
| | | | | | ||||||
| | | * | | Make liberal use of IdString.in() | Eddie Hung | 2019-08-06 | 2 | -2/+2 | |
| | | | | | ||||||
| | * | | | Merge pull request #1263 from ucb-bar/firrtl_err_on_unsupported_cell | Clifford Wolf | 2019-08-10 | 1 | -1/+1 | |
| | |\ \ \ | | | | | | | | | | | FIRRTL error on unsupported cell | |||||
| | | * \ \ | Merge branch 'master' into firrtl_err_on_unsupported_cell | Jim Lawson | 2019-08-07 | 9 | -116/+287 | |
| | | |\ \ \ | | | | |/ | | | |/| | | | | | | | | | | | # Conflicts: # backends/firrtl/firrtl.cc | |||||
| | | * | | | Call log_error() instead of log_warning() on unsupported cell type in FIRRTL ↵ | Jim Lawson | 2019-07-24 | 1 | -1/+1 | |
| | | | | | | | | | | | | | | | | | | | | | backend. | |||||
| | * | | | | Run "clean -purge" on holes_module in its own design | Eddie Hung | 2019-08-07 | 1 | -6/+11 | |
| | | |/ / | |/| | | ||||||
| | * | | | Merge pull request #1240 from ucb-bar/firrtl-properties+pow+xnor | Clifford Wolf | 2019-08-07 | 1 | -93/+203 | |
| | |\ \ \ | | | | | | | | | | | Support explicit FIRRTL properties for better accommodation of FIRRTL/Verilog semantic differences. | |||||
| | | * | | | Support explicit FIRRTL properties for better accommodation of ↵ | Jim Lawson | 2019-07-31 | 1 | -93/+203 | |
| | | |/ / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | FIRRTL/Verilog semantic differences. Use FIRRTL spec vlaues for definition of FIRRTL widths. Added support for '$pos`, `$pow` and `$xnor` cells. Enable tests/simple/operators.v since all operators tested there are now supported. Disable FIRRTL tests of tests/simple/{defvalue.sv,implicit_ports.v,wandwor.v} since they currently generate FIRRTL compilation errors. | |||||
| | * | | | Merge pull request #1241 from YosysHQ/clifford/jsonfix | David Shah | 2019-08-07 | 1 | -13/+37 | |
| | |\ \ \ | | |_|/ | |/| | | Improved JSON attr/param encoding | |||||
| | | * | | Implement improved JSON attr/param encoding | Clifford Wolf | 2019-08-01 | 1 | -13/+37 | |
| | | |/ | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| | * | | Add $_NMUX_, add "abc -g cmos", add proper cmos cell costs | Clifford Wolf | 2019-08-06 | 6 | -3/+40 | |
| | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| | * | | Merge pull request #1238 from mmicko/vsbuild_fix | Clifford Wolf | 2019-08-02 | 1 | -1/+1 | |
| | |\ \ | | | | | | | | | Visual Studio build fix | |||||
| | | * | | Visual Studio build fix | Miodrag Milanovic | 2019-07-31 | 1 | -1/+1 | |
| | | |/ | ||||||
| | * / | Fix formatting for msys2 mingw build using GetSize | Miodrag Milanovic | 2019-08-01 | 1 | -6/+6 | |
| | |/ | ||||||
| | * | Merge pull request #1203 from whitequark/write_verilog-zero-width-values | Clifford Wolf | 2019-07-18 | 1 | -1/+2 | |
| | |\ | | | | | | | write_verilog: dump zero width constants correctly | |||||
| | | * | write_verilog: dump zero width constants correctly. | whitequark | 2019-07-16 | 1 | -1/+2 | |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Before this commit, zero width constants were dumped as "" (empty string). Unfortunately, 1364-2005 5.2.3.3 indicates that an empty string is equivalent to "\0", and is 8 bits wide, so that's wrong. After this commit, a replication operation with a count of zero is used instead, which is explicitly permitted per 1364-2005 5.1.14, and is defined to have size zero. (Its operand has to have a non-zero size for it to be legal, though.) Fixes #948 (again). | |||||
| | * | | Remove old $pmux_safe code from write_verilog | Clifford Wolf | 2019-07-17 | 1 | -5/+4 | |
| | |/ | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| | * | smt: handle failure of setrlimit syscall | N. Engelhardt | 2019-07-15 | 1 | -1/+5 | |
| | | | ||||||
| | * | Merge pull request #1172 from whitequark/write_verilog-Sa-as-qmark | Clifford Wolf | 2019-07-11 | 1 | -2/+8 | |
| | |\ | | | | | | | write_verilog: write RTLIL::Sa aka - as Verilog ? | |||||
| | | * | write_verilog: write RTLIL::Sa aka - as Verilog ?. | whitequark | 2019-07-09 | 1 | -2/+8 | |
| | | | | | | | | | | | | | | | | | | | | | | Currently, the only ways (determined by grepping for regex \bSa\b) to end up with RTLIL::Sa in a netlist is by reading a Verilog constant with ? in it as a part of case, or by running certain FSM passes. Both of these cases should be round-tripped back to ? in Verilog. | |||||
| * | | | abc_flop to also get topologically sorted | Eddie Hung | 2019-07-10 | 1 | -11/+10 | |
| | | | | ||||||
| * | | | Fix clk_pol for FD*_1 | Eddie Hung | 2019-07-10 | 1 | -1/+0 | |
| | | | | ||||||
| * | | | Fix spacing | Eddie Hung | 2019-07-10 | 1 | -1/+1 | |
| | | | | ||||||
| * | | | Change how to specify flops to ABC again | Eddie Hung | 2019-07-10 | 1 | -10/+20 | |
| | | | | ||||||
| * | | | Use split_tokens() | Eddie Hung | 2019-07-10 | 1 | -17/+11 | |
| | | | | ||||||
| * | | | Merge remote-tracking branch 'origin/master' into xaig_dff | Eddie Hung | 2019-07-10 | 3 | -15/+34 | |
| |\| | | ||||||
| | * | | Merge pull request #1175 from whitequark/write_verilog-fix-case-attr-position | Clifford Wolf | 2019-07-09 | 1 | -3/+2 | |
| | |\ \ | | | | | | | | | write_verilog: fix placement of case attributes | |||||
| | | * | | write_verilog: fix placement of case attributes. NFC. | whitequark | 2019-07-09 | 1 | -3/+2 | |
| | | |/ | ||||||
| | * | | Merge pull request #1170 from YosysHQ/eddie/fix_double_underscore | Eddie Hung | 2019-07-09 | 1 | -4/+6 | |
| | |\ \ | | |/ | |/| | Rename __builtin_bswap32 -> bswap32 | |||||
| | | * | Rename __builtin_bswap32 -> bswap32 | Eddie Hung | 2019-07-09 | 1 | -4/+6 | |
| | | | | ||||||
| | * | | verilog_backend: dump attributes on SwitchRule. | whitequark | 2019-07-08 | 1 | -0/+1 | |
| | | | | | | | | | | | | | This appears to be an omission. | |||||
| | * | | verilog_backend: dump attributes on CaseRule, as comments. | whitequark | 2019-07-08 | 1 | -6/+10 | |
| | | | | | | | | | | | | | Attributes are not permitted in that position by Verilog grammar. | |||||
| | * | | Allow attributes on individual switch cases in RTLIL. | whitequark | 2019-07-08 | 1 | -0/+5 | |
| | |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The parser changes are slightly awkward. Consider the following IL: process $0 <point 1> switch \foo <point 2> case 1'1 assign \bar \baz <point 3> ... case end end Before this commit, attributes are valid in <point 1>, and <point 3> iff it is immediately followed by a `switch`. (They are essentially attached to the switch.) But, after this commit, and because switch cases do not have an ending delimiter, <point 3> becomes ambiguous: the attribute could attach to either the following `case`, or to the following `switch`. This isn't expressible in LALR(1) and results in a reduce/reduce conflict. To address this, attributes inside processes are now valid anywhere inside the process: in <point 1> and <point 3> a part of case body, and in <point 2> as a separate rule. As a consequence, attributes can now precede `assign`s, which is made illegal in the same way it is illegal to attach attributes to `connect`. Attributes are tracked separately from the parser state, so this does not affect collection of attributes at all, other than allowing them on `case`s. The grammar change serves purely to allow attributes in more syntactic places. | |||||
| | * | write_xaiger to treat unknown cell connections as keep-s | Eddie Hung | 2019-07-02 | 1 | -6/+14 | |
| | | | ||||||
| * | | Safe side: all flops have different mergeability class | Eddie Hung | 2019-07-02 | 1 | -1/+1 | |
| | | | ||||||
| * | | Refactor and cope with new abc_flop format | Eddie Hung | 2019-07-01 | 1 | -16/+38 | |
| | | | ||||||
| * | | Merge remote-tracking branch 'origin/master' into xaig_dff | Eddie Hung | 2019-07-01 | 7 | -102/+204 | |
| |\| | ||||||
| | * | Add generic __builtin_bswap32 function | Eddie Hung | 2019-06-28 | 1 | -0/+15 | |
| | | | ||||||
| | * | Also fix write_aiger for UB | Eddie Hung | 2019-06-28 | 1 | -26/+26 | |
| | | | ||||||
| | * | Fix more potential for undefined behaviour due to container invalidation | Eddie Hung | 2019-06-28 | 1 | -6/+10 | |
| | | | ||||||
| | * | Refactor for one "abc_carry" attribute on module | Eddie Hung | 2019-06-27 | 1 | -42/+40 | |
| | | | ||||||
| | * | Merge origin/master | Eddie Hung | 2019-06-27 | 2 | -4/+31 | |
| | | | ||||||
| | * | Improve debugging message for comb loops | Eddie Hung | 2019-06-26 | 1 | -4/+6 | |
| | | | ||||||
| | * | Merge remote-tracking branch 'origin/master' into xaig | Eddie Hung | 2019-06-24 | 1 | -0/+4 | |
| | |\ | ||||||
| | | * | Fix json formatting | Miodrag Milanovic | 2019-06-21 | 1 | -1/+1 | |
| | | | | ||||||
| | | * | Add upto and offset to JSON ports | Miodrag Milanovic | 2019-06-21 | 1 | -0/+4 | |
| | | | | ||||||
| | * | | Carry in/out box ordering now move to end, not swap with end | Eddie Hung | 2019-06-22 | 1 | -26/+34 | |
| | | | | ||||||
| | * | | Merge remote-tracking branch 'origin/master' into xaig | Eddie Hung | 2019-06-21 | 1 | -0/+4 | |
| | |\| | ||||||
| | | * | Added JSON upto and offset | Clifford Wolf | 2019-06-21 | 1 | -0/+4 | |
| | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| | | * | Fix gcc invalidation behaviour for write_aiger | Eddie Hung | 2019-06-20 | 1 | -1/+2 | |
| | | | | ||||||
 |
index : iCE40/yosys | |
| [no description] |
| aboutsummaryrefslogtreecommitdiffstats |