| Commit message (Expand) | Author | Age | Files | Lines |
* | Added "yosys-smt2-wire" tag support to smt2 back-end | Clifford Wolf | 2015-08-31 | 1 | -0/+2 |
* | Fixed generation of smt2 concat statements | Clifford Wolf | 2015-08-15 | 1 | -3/+5 |
* | Another block of spelling fixes | Larry Doolittle | 2015-08-14 | 3 | -4/+4 |
* | Re-created command-reference-manual.tex, copied some doc fixes to online help | Clifford Wolf | 2015-08-14 | 1 | -3/+3 |
* | Spell check (by Larry Doolittle) | Clifford Wolf | 2015-08-14 | 2 | -3/+3 |
* | Added "write_smt2 -regs" | Clifford Wolf | 2015-08-12 | 1 | -7/+36 |
* | Added SMV back-end 'test_cells.sh' script | Clifford Wolf | 2015-08-12 | 1 | -0/+33 |
* | Use MEMID as name for $mem cell | Clifford Wolf | 2015-08-09 | 1 | -1/+6 |
* | Remove some very strange whitespace in btor.cc (by Larry Doolittle) | Clifford Wolf | 2015-08-05 | 1 | -7/+7 |
* | Bugfix in SMV back-end for partially unassigned wires | Clifford Wolf | 2015-08-05 | 1 | -4/+16 |
* | Added $assert support to SMV back-end | Clifford Wolf | 2015-08-04 | 1 | -4/+21 |
* | Improvements in BLIF back-end | Clifford Wolf | 2015-07-29 | 1 | -5/+84 |
* | Fixed trailing whitespaces | Clifford Wolf | 2015-07-02 | 13 | -114/+114 |
* | Added init support to SMV back-end | Clifford Wolf | 2015-06-19 | 1 | -1/+3 |
* | Progress in SMV back-end | Clifford Wolf | 2015-06-19 | 1 | -64/+115 |
* | Progress in SMV back-end | Clifford Wolf | 2015-06-19 | 1 | -13/+59 |
* | Progress in SMV back-end | Clifford Wolf | 2015-06-18 | 1 | -24/+94 |
* | Progress in SMV back-end | Clifford Wolf | 2015-06-17 | 1 | -11/+72 |
* | Progress in SMV back-end | Clifford Wolf | 2015-06-17 | 1 | -11/+64 |
* | Progress in SMV back-end | Clifford Wolf | 2015-06-16 | 1 | -3/+46 |
* | Progress in SMV back-end | Clifford Wolf | 2015-06-15 | 1 | -2/+95 |
* | Progress in SMV back-end | Clifford Wolf | 2015-06-15 | 1 | -7/+85 |
* | Added "write_smv" skeleton | Clifford Wolf | 2015-06-15 | 2 | -0/+261 |
* | Removed debug code from write_smt2 | Clifford Wolf | 2015-06-14 | 1 | -2/+0 |
* | Added write_smt2 -mem | Clifford Wolf | 2015-06-14 | 1 | -80/+157 |
* | Fixed cstr_buf for std::string with small string optimization | Clifford Wolf | 2015-06-11 | 2 | -2/+2 |
* | Improvements in cellaigs.cc and "json -aig" | Clifford Wolf | 2015-06-11 | 1 | -6/+63 |
* | AigMaker refactoring | Clifford Wolf | 2015-06-10 | 1 | -1/+1 |
* | Added "json -aig" | Clifford Wolf | 2015-06-10 | 1 | -9/+63 |
* | $mem cell in verilog backend : grouped writes by clock | luke whittlesey | 2015-06-08 | 1 | -54/+108 |
* | Bug fix in $mem verilog backend + changed tests/bram flow of make test. | luke whittlesey | 2015-06-04 | 1 | -14/+16 |
* | Improvements in BLIF front-end | Clifford Wolf | 2015-05-24 | 1 | -0/+1 |
* | Some fixes for $mem in verilog back-end | Clifford Wolf | 2015-05-20 | 1 | -19/+23 |
* | Merge pull request #63 from wluker/verilog-backend-mem | Clifford Wolf | 2015-05-11 | 1 | -1/+2 |
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| * | Fixed bug in $mem cell verilog code generation. | luke whittlesey | 2015-05-11 | 1 | -11/+12 |
* | | Disabled broken $mem support in verilog backend | Clifford Wolf | 2015-05-10 | 1 | -11/+11 |
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* | Made changes recommended by Clifford Wolf ... | luke whittlesey | 2015-05-10 | 1 | -22/+11 |
* | Verilog backend for $mem cells should now be able to handle different | luke whittlesey | 2015-05-08 | 1 | -50/+105 |
* | Added support for $mem cells in the verilog backend. | luke whittlesey | 2015-05-07 | 1 | -1/+120 |
* | Minor fixes in handling of "init" attribute | Clifford Wolf | 2015-04-09 | 1 | -7/+7 |
* | Removed "techmap -share_map" (use "-map +/filename" instead) | Clifford Wolf | 2015-04-08 | 1 | -1/+1 |
* | Added "port_directions" to write_json output | Clifford Wolf | 2015-04-06 | 1 | -0/+20 |
* | Added "init" attribute support to verilog backend | Clifford Wolf | 2015-04-04 | 1 | -0/+5 |
* | Update README | Ahmed Irfan | 2015-04-03 | 1 | -1/+1 |
* | Delete btor.ys | Ahmed Irfan | 2015-04-03 | 1 | -18/+0 |
* | Update README | Ahmed Irfan | 2015-04-03 | 1 | -1/+1 |
* | separated memory next from write cell | Ahmed Irfan | 2015-04-03 | 1 | -7/+55 |
* | Added Verilog backend $dffsr support | Clifford Wolf | 2015-03-18 | 1 | -1/+51 |
* | Documentation for JSON format, added attributes | Clifford Wolf | 2015-03-06 | 1 | -16/+156 |
* | Json bugfix | Clifford Wolf | 2015-03-03 | 1 | -1/+1 |