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* Add $shiftx support to verilog front-endClifford Wolf2017-10-071-0/+17
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* Rename "write_verilog -nobasenradix" to "write_verilog -decimal"Clifford Wolf2017-10-031-16/+13
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* Fixed wrong declaration in Verilog backenddh732017-10-011-3/+3
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* Adding Cyclone IV (E, GX), Arria 10, Cyclone V and LPM functions (ALTPLL and ↵dh732017-10-011-3/+16
| | | | M9K); M9K is not finished yet. Achronix Speedster also in this commit. Both Arria10 and Speedster-i are still experimental due complexity, but you can experiment around those devices right now
* Fix bug in write_smt2 (export logic driving hierarchical cells before ↵Clifford Wolf2017-08-251-34/+34
| | | | exporting regs)
* Add "yosys-smtbmc --smtc-init --smtc-top --noinit"Clifford Wolf2017-08-041-20/+66
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* Add verilator support to testbenches generated by yosys-smtbmcClifford Wolf2017-07-211-3/+15
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* Generate FSM-style testbenches in smtbmcClifford Wolf2017-07-121-5/+23
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* Fix the fixed handling of x-bits in EDIF back-endClifford Wolf2017-07-111-1/+0
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* Fix handling of x-bits in EDIF back-endClifford Wolf2017-07-111-1/+11
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* Add attributes and parameter support to JSON front-endClifford Wolf2017-07-101-0/+2
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* Change s/asserts/assertions/ in yosys-smtbmc log messagesClifford Wolf2017-07-071-2/+2
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* Add "yosys-smtbmc --presat"Clifford Wolf2017-07-071-3/+23
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* Fix generation of multiple outputs for same AIG node in write_aigerClifford Wolf2017-07-051-13/+30
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* Add write_table commandClifford Wolf2017-07-052-0/+123
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* Remove unneeded delays in smtbmc vlogtbClifford Wolf2017-07-031-1/+1
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* Include output ports with constant driver in AIGER outputClifford Wolf2017-07-031-2/+18
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* Add "yosys-smtbmc --vlogtb-top"Clifford Wolf2017-07-011-15/+32
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* Fix smtbmc vlogtb bug in $anyseq handlingClifford Wolf2017-07-011-3/+3
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* Fix generation of vlogtb output in yosys-smtbmc for "rand reg" and "rand ↵Clifford Wolf2017-06-073-4/+53
| | | | const reg"
* Fix AIGER back-end for multiple symbols per input/latch/output/propertyClifford Wolf2017-05-301-8/+20
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* Improve write_aiger handling of unconnected nets and constantsClifford Wolf2017-05-281-7/+61
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* Change default smt2 solver to yices (Yices 2 has switched its license to GPL)Clifford Wolf2017-05-271-4/+4
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* Add workaround for CBMC bug to SimpleC back-endClifford Wolf2017-05-171-1/+3
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* Add $_ANDNOT_ and $_ORNOT_ gatesClifford Wolf2017-05-175-14/+36
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* Add <modname>_init() function generator to simpleC back-endClifford Wolf2017-05-162-88/+152
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* Improve simplec back-endClifford Wolf2017-05-161-1/+1
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* Improve simplec back-endClifford Wolf2017-05-151-42/+44
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* Improve simplec back-endClifford Wolf2017-05-143-3/+49
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* Improve simplec back-endClifford Wolf2017-05-131-25/+60
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* Improve simplec back-endClifford Wolf2017-05-123-12/+78
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* Added support for more gate types to simplec back-endClifford Wolf2017-05-121-1/+88
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* Add first draft of simple C back-endClifford Wolf2017-05-126-0/+623
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* Fix boolector support in yosys-smtbmcClifford Wolf2017-05-081-18/+18
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* Add "write_smt2 -stdt" modeClifford Wolf2017-03-202-37/+84
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* Add generation of logic cells to EDIF back-end runtest.pyClifford Wolf2017-03-191-2/+6
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* Fix EDIF: portRef member 0 is always the MSB bitClifford Wolf2017-03-192-13/+14
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* Add simple EDIF test case generator and checkerClifford Wolf2017-03-181-0/+113
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* Improve smt2 encodings of assert/assume/cover, better wire_smt2 help msgClifford Wolf2017-03-042-33/+87
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* Add write_aiger $anyseq supportClifford Wolf2017-03-021-0/+7
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* Use hex addresses in smtbmc vcd mem tracesClifford Wolf2017-02-281-1/+1
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* Add smtbmc support for memory vcd dumpingClifford Wolf2017-02-261-0/+98
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* Fix extra newline bug in write_smt2Clifford Wolf2017-02-261-1/+1
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* Fix bug in smtio unroll codeClifford Wolf2017-02-261-3/+2
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* Fix assert checking in "yosys-smtbmc -c --append"Clifford Wolf2017-02-261-1/+1
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* Improve (and fix for stbv mode) SMT2 memory APIClifford Wolf2017-02-263-47/+51
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* Add support for "yosys-smtbmc -c --append"Clifford Wolf2017-02-251-1/+13
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* Improve "write_edif" help messageClifford Wolf2017-02-251-7/+2
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* Move EdifNames out of double-private namespaceClifford Wolf2017-02-251-48/+45
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* Clean up edif code, swap bit indexing of "upto" portsClifford Wolf2017-02-251-17/+35
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