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| author | Clifford Wolf <clifford@clifford.at> | 2017-07-11 17:38:19 +0200 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2017-07-11 17:38:19 +0200 |
| commit | 479be3cec7a4ae5277720e75e215bc3d577261a9 (patch) | |
| tree | 1393025e15e87b8ca8d058420766aa8e7755d5c0 /backends | |
| parent | 9557fd2a3607261a612cabef47b0877dc59f506c (diff) | |
| download | yosys-479be3cec7a4ae5277720e75e215bc3d577261a9.tar.gz yosys-479be3cec7a4ae5277720e75e215bc3d577261a9.tar.bz2 yosys-479be3cec7a4ae5277720e75e215bc3d577261a9.zip | |
Fix handling of x-bits in EDIF back-end
Diffstat (limited to 'backends')
| -rw-r--r-- | backends/edif/edif.cc | 12 |
1 files changed, 11 insertions, 1 deletions
diff --git a/backends/edif/edif.cc b/backends/edif/edif.cc index 229b039b9..995aa2091 100644 --- a/backends/edif/edif.cc +++ b/backends/edif/edif.cc @@ -374,7 +374,17 @@ struct EdifBackend : public Backend { } for (auto &it : net_join_db) { RTLIL::SigBit sig = it.first; - if (sig.wire == NULL && sig != RTLIL::State::S0 && sig != RTLIL::State::S1) + if (sig.wire == NULL && sig != RTLIL::State::S0 && sig != RTLIL::State::S1) { + if (sig == RTLIL::State::Sx) { + for (auto &ref : it.second) + log_warning("Exporting x-bit on %s as zero bit.\n", ref.c_str()); + sig = RTLIL::State::S0; + } else { + for (auto &ref : it.second) + log_error("Don't know how to handle %s on %s.\n", log_signal(sig), ref.c_str()); + log_abort(); + } + } log_abort(); std::string netname; if (sig == RTLIL::State::S0) |