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| author | Clifford Wolf <clifford@clifford.at> | 2017-03-19 14:53:28 +0100 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2017-03-19 14:53:28 +0100 |
| commit | 850f8299a9374ae4b9caeca8b6cd888be7c0a406 (patch) | |
| tree | 4f332696647cb6579e6b2a18b3110d08271d0aaf /backends | |
| parent | 1390e9a0a7d4872e24a9fe53e258b8097932392a (diff) | |
| download | yosys-850f8299a9374ae4b9caeca8b6cd888be7c0a406.tar.gz yosys-850f8299a9374ae4b9caeca8b6cd888be7c0a406.tar.bz2 yosys-850f8299a9374ae4b9caeca8b6cd888be7c0a406.zip | |
Fix EDIF: portRef member 0 is always the MSB bit
Diffstat (limited to 'backends')
| -rw-r--r-- | backends/edif/edif.cc | 9 | ||||
| -rw-r--r-- | backends/edif/runtest.py | 18 |
2 files changed, 14 insertions, 13 deletions
diff --git a/backends/edif/edif.cc b/backends/edif/edif.cc index e0eea85c9..229b039b9 100644 --- a/backends/edif/edif.cc +++ b/backends/edif/edif.cc @@ -317,10 +317,7 @@ struct EdifBackend : public Backend { *f << stringf(" (port (array %s %d) (direction %s))\n", EDIF_DEFR(wire->name, port_rename, b[0], b[1]), wire->width, dir); for (int i = 0; i < wire->width; i++) { RTLIL::SigSpec sig = sigmap(RTLIL::SigSpec(wire, i)); - if (wire->upto) - net_join_db[sig].insert(stringf("(portRef (member %s %d))", EDIF_REF(wire->name), GetSize(wire)-i-1)); - else - net_join_db[sig].insert(stringf("(portRef (member %s %d))", EDIF_REF(wire->name), i)); + net_join_db[sig].insert(stringf("(portRef (member %s %d))", EDIF_REF(wire->name), GetSize(wire)-i-1)); } } } @@ -363,11 +360,11 @@ struct EdifBackend : public Backend { else if (sig.size() == 1) net_join_db[sig[i]].insert(stringf("(portRef %s (instanceRef %s))", EDIF_REF(p.first), EDIF_REF(cell->name))); else { - int member_idx = i; + int member_idx = GetSize(sig)-i-1; auto m = design->module(cell->type); if (m) { auto w = m->wire(p.first); - if (w && w->upto) + if (w) member_idx = GetSize(w)-i-1; } net_join_db[sig[i]].insert(stringf("(portRef (member %s %d) (instanceRef %s))", diff --git a/backends/edif/runtest.py b/backends/edif/runtest.py index ced5fda5c..c842e6784 100644 --- a/backends/edif/runtest.py +++ b/backends/edif/runtest.py @@ -5,6 +5,7 @@ import numpy as np enable_upto = True enable_offset = True +enable_hierarchy = True def make_module(f, modname, width, subs): print("module %s (A, B, C, X, Y, Z);" % modname, file=f) @@ -60,13 +61,16 @@ def make_module(f, modname, width, subs): print("endmodule", file=f) with open("test_top.v", "w") as f: - make_module(f, "sub1", 2, {}) - make_module(f, "sub2", 3, {}) - make_module(f, "sub3", 4, {}) - make_module(f, "sub4", 8, {"sub1": 2, "sub2": 3, "sub3": 4}) - make_module(f, "sub5", 8, {"sub1": 2, "sub2": 3, "sub3": 4}) - make_module(f, "sub6", 8, {"sub1": 2, "sub2": 3, "sub3": 4}) - make_module(f, "top", 32, {"sub4": 8, "sub5": 8, "sub6": 8}) + if enable_hierarchy: + make_module(f, "sub1", 2, {}) + make_module(f, "sub2", 3, {}) + make_module(f, "sub3", 4, {}) + make_module(f, "sub4", 8, {"sub1": 2, "sub2": 3, "sub3": 4}) + make_module(f, "sub5", 8, {"sub1": 2, "sub2": 3, "sub3": 4}) + make_module(f, "sub6", 8, {"sub1": 2, "sub2": 3, "sub3": 4}) + make_module(f, "top", 32, {"sub4": 8, "sub5": 8, "sub6": 8}) + else: + make_module(f, "top", 32, {}) os.system("set -x; ../../yosys -p 'prep -top top; write_edif -pvector par test_syn.edif' test_top.v") |