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* Updated manual/command-reference-manual.texClifford Wolf2013-12-281-1/+1
* Added support for non-const === and !== (for miter circuits)Clifford Wolf2013-12-271-6/+8
* Replaced signed_parameters API with CONST_FLAG_SIGNEDClifford Wolf2013-12-042-2/+2
* Replaced RTLIL::Const::str with generic decoder methodClifford Wolf2013-12-043-18/+24
* Fixed gentb_constant handling in autotest backendClifford Wolf2013-12-041-2/+2
* Added dump -m and -n optionsClifford Wolf2013-11-292-54/+89
* Added proper dumping of signed/unsigned parameters to verilog backendClifford Wolf2013-11-241-4/+6
* Added support for signed parameters in ilangClifford Wolf2013-11-241-1/+1
* Remove auto_wire framework (smarter than the verilog standard)Clifford Wolf2013-11-241-2/+0
* Added modelsim support to autotestClifford Wolf2013-11-241-6/+6
* Added "top" attribute to mark top module in hierarchyClifford Wolf2013-11-243-0/+15
* Renamed "placeholder" to "blackbox"Clifford Wolf2013-11-225-14/+14
* Implemented $_DFFSR_ expression generator in verilog backendClifford Wolf2013-11-211-1/+44
* Major improvements in mem2reg and added "init" sync rulesClifford Wolf2013-11-211-0/+1
* Silenced a gcc warning in spice backendClifford Wolf2013-11-091-1/+1
* Improved comments on topological sort in edif backendClifford Wolf2013-11-041-3/+4
* Added simple topological sort to edif backendClifford Wolf2013-11-031-2/+30
* Write yosys version to output filesClifford Wolf2013-11-035-6/+10
* Merge branch 'master' of github.com:cliffordwolf/yosysClifford Wolf2013-11-031-3/+5
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| * Ignore explicit unconnected ports in intersynth backendClifford Wolf2013-11-031-3/+5
* | Added placeholder check to dfflibmap and cleaned up some other placeholder ch...Clifford Wolf2013-10-311-1/+1
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* Fixed hex string generation bug in edif backendClifford Wolf2013-10-271-4/+4
* Added support for complex set-reset flip-flops in proc_dffClifford Wolf2013-10-241-1/+6
* Fixed handling of boolean attributes (backends)Clifford Wolf2013-10-246-10/+10
* Fixed handling of boolean attributes (kernel)Clifford Wolf2013-10-241-4/+4
* Added $_SR_[PN][PN]_, $_DFFSR_[PN][PN][PN]_, $_DLATCH_[PN]_Clifford Wolf2013-10-181-0/+1
* Added $sr, $dffsr and $dlatch cell typesClifford Wolf2013-10-181-28/+1
* Added -buf, -true and -false options to blif backendClifford Wolf2013-10-171-2/+40
* Improvements in EDIF backendClifford Wolf2013-09-172-2/+41
* Added additional options to BLIF backendClifford Wolf2013-09-151-15/+60
* Added BLIF backendClifford Wolf2013-09-152-0/+245
* A couple of small fixes in SPICE backendClifford Wolf2013-09-151-6/+18
* Added spice testbench to techlibs/cmosClifford Wolf2013-09-141-3/+0
* Added spice backendClifford Wolf2013-09-142-0/+228
* Merge branch 'master' of github.com:cliffordwolf/yosysClifford Wolf2013-09-031-8/+31
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| * Encode large (>32 bits) parameters as hex string in edif backendClifford Wolf2013-08-281-3/+16
| * Improved edif backendClifford Wolf2013-08-271-8/+18
* | Added -selected option to various backendsClifford Wolf2013-09-033-9/+58
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* More explicit integer output in verilog backendClifford Wolf2013-08-221-2/+2
* Added correct encoding of identifiers in EDIF backendClifford Wolf2013-08-221-13/+61
* Added edif backend (still under construction)Clifford Wolf2013-08-222-0/+202
* Fixed generation of newlines in "dump" outputClifford Wolf2013-06-101-3/+4
* Added "dump" command (part ilang backend)Clifford Wolf2013-06-022-13/+103
* Implemented proper handling of stub placeholder modulesClifford Wolf2013-03-281-6/+18
* Added -notypes option to intersynth backendClifford Wolf2013-03-241-7/+18
* Fixed gcc build (intersynth backend)Clifford Wolf2013-03-231-14/+14
* Various improvements in intersynth backendClifford Wolf2013-03-231-9/+56
* Added intersynth backendClifford Wolf2013-03-232-0/+141
* Avoid verilog-2k in verilog backendClifford Wolf2013-03-211-0/+17
* More support code for $sr cellsClifford Wolf2013-03-141-1/+29