| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | Add $_ANDNOT_ and $_ORNOT_ gates | Clifford Wolf | 2017-05-17 | 1 | -4/+6 |
| * | Cleanups and fixed in write_verilog regarding reg init | Clifford Wolf | 2016-11-16 | 1 | -15/+61 |
| * | Added hex constant support to write_verilog | Clifford |
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index : iCE40/yosys | |
| clone of https://github.com/YosysHQ/yosys |
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