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author | Larry Doolittle <ldoolitt@recycle.lbl.gov> | 2015-08-14 13:23:01 -0700 |
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committer | Clifford Wolf <clifford@clifford.at> | 2015-08-14 23:27:05 +0200 |
commit | 6c00704a5ef09be46b1f05e2be477e493f37dd38 (patch) | |
tree | a64fb142c62fd5cd49a9928b5125ea4e133f4471 /backends/verilog/verilog_backend.cc | |
parent | 022f570563d8b067e9638bc91bbd168f4c5cb817 (diff) | |
download | yosys-6c00704a5ef09be46b1f05e2be477e493f37dd38.tar.gz yosys-6c00704a5ef09be46b1f05e2be477e493f37dd38.tar.bz2 yosys-6c00704a5ef09be46b1f05e2be477e493f37dd38.zip |
Another block of spelling fixes
Smaller this time
Diffstat (limited to 'backends/verilog/verilog_backend.cc')
-rw-r--r-- | backends/verilog/verilog_backend.cc | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/backends/verilog/verilog_backend.cc b/backends/verilog/verilog_backend.cc index 28c54ce0b..c04389f63 100644 --- a/backends/verilog/verilog_backend.cc +++ b/backends/verilog/verilog_backend.cc @@ -17,7 +17,7 @@ * * --- * - * A simple and straightforward verilog backend. + * A simple and straightforward Verilog backend. * * Note that RTLIL processes can't always be mapped easily to a Verilog * process. Therefore this frontend should only be used to export a @@ -966,7 +966,7 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell) n += wen_width; } } - // Output verilog that looks something like this: + // Output Verilog that looks something like this: // reg [..] _3_; // always @(posedge CLK2) begin // _3_ <= memory[D1ADDR]; |